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1. 发明授权

US07307009B2 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US07307009B2
公开(公告)日：2007-12-11
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

2. 发明授权

US06849531B1 Phosphoric acid free process for polysilicon gate definition 失效
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US06849531B1
公开(公告)日：2005-02-01
申请号：US10718876
申请日：2003-11-21
申请人： Li-Te S. Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te S. Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a gate structure for a MOSFET device featuring the employment of dual anti-reflective coating (ARC) layers to enhance gate structure resolution, and featuring a dry procedure for removal of all ARC layers avoiding the use of hot phosphoric acid, has been developed. After formation of a polysilicon layer on an underlying silicon dioxide gate insulator layer, a capping silicon oxide, a dielectric ARC layer, and an overlying organic ARC layer are deposited. A photoresist shape is formed and used as an etch mask to allow a first anisotropic RIE procedure to define the desired gate structure shape in the dual ARC layers and in the capping silicon oxide layer. After removal of the photoresist shape and the overlying organic ARC layer a second anisotropic RIE procedure is used to define a desired polysilicon gate structure, with the second anisotropic RIE procedure also resulting in the removal of the dielectric ARC shape. A final hydrofluoric acid type solution is then used to remove the capping silicon oxide shape as well as to remove the portions of the silicon dioxide gate insulator layer not covered by the polysilicon gate structure.
摘要翻译：一种限定用于MOSFET器件的栅极结构的方法，其特征在于采用双抗反射涂层（ARC）层以增强栅极结构分辨率，并且具有用于去除所有ARC层的干法以避免使用热磷酸，具有已经开发在下面的二氧化硅栅极绝缘体层上形成多晶硅层之后，沉积覆盖氧化硅，电介质ARC层和上覆的有机ARC层。形成光致抗蚀剂形状并用作蚀刻掩模，以允许第一各向异性RIE程序在双ARC层和封盖氧化硅层中限定所需的栅极结构形状。在除去光致抗蚀剂形状和上覆的有机ARC层之后，使用第二各向异性RIE程序来限定期望的多晶硅栅极结构，其中第二各向异性RIE程序也导致去除电介质ARC形状。然后使用最终的氢氟酸型溶液去除封端氧化硅形状以及去除未被多晶硅栅极结构覆盖的二氧化硅栅极绝缘体层的部分。

3. 发明申请

US20050118755A1 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US20050118755A1
公开(公告)日：2005-06-02
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

4. 发明授权

US06869868B2 Method of fabricating a MOSFET device with metal containing gate structures 有权
标题翻译：制造具有含金属栅极结构的MOSFET器件的方法
公开(公告)号：US06869868B2
公开(公告)日：2005-03-22
申请号：US10318459
申请日：2002-12-13
申请人： Hsien-Kuang Chiu , Fang-Cheng Chen , Haur-Ywh Chen , Hun-Jan Tao , Yuan-Hung Chiu
发明人： Hsien-Kuang Chiu , Fang-Cheng Chen , Haur-Ywh Chen , Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/4763
CPC分类号： H01L29/785 , H01L21/28088 , H01L29/42384 , H01L29/4966 , H01L29/665 , H01L29/66795
摘要： A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.
摘要翻译：已经开发了形成用于平面MOSFET器件的复合栅极结构以及用于垂直双栅极FINFET器件的方法。该方法具有由上覆硅栅极结构形状和下面的氮化钛栅极结构形状组成的复合栅极结构。与仅由多晶硅形成的对应栅极结构相比，氮化钛部件允许较低的功函数，因此降低器件工作电压。采用新颖的两步栅极结构定义方法，其特征在于用于定义多晶硅栅极结构形状的各向异性第一蚀刻工艺，随后是用于定义氮化钛栅极结构形状的湿式或干式同位素第二蚀刻工艺。

5. 发明授权

US06867084B1 Gate structure and method of forming the gate dielectric with mini-spacer 有权
标题翻译：用微型间隔物形成栅极电介质的栅结构和方法
公开(公告)号：US06867084B1
公开(公告)日：2005-03-15
申请号：US10263541
申请日：2002-10-03
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

6. 发明申请

US20050127459A1 Novel gate structure and method of forming the gate dielectric with mini-spacer 审中-公开
标题翻译：具有微型间隔物形成栅极电介质的新型栅极结构和方法
公开(公告)号：US20050127459A1
公开(公告)日：2005-06-16
申请号：US11048205
申请日：2005-02-01
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

7. 发明授权

US06794302B1 Dynamic feed forward temperature control to achieve CD etching uniformity 失效
标题翻译：动态前馈温度控制实现CD蚀刻均匀性
公开(公告)号：US06794302B1
公开(公告)日：2004-09-21
申请号：US10393909
申请日：2003-03-20
申请人： Li-Shiun Chen , Ming-Ching Chang , Huan-Just Lin , Li-Te S. Lin , Yung-Hog Chiu , Hun-Jan Tao
发明人： Li-Shiun Chen , Ming-Ching Chang , Huan-Just Lin , Li-Te S. Lin , Yung-Hog Chiu , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01J37/32935 , H01L21/32135 , H01L21/32137
摘要： A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.
摘要翻译：一种用于在包括具有包括图案特征的工艺表面的半导体晶片的等离子体蚀刻工艺中补偿半导体工艺晶片表面上的CD变化的方法; 执行第一等离子体蚀刻工艺，其中半导体晶片被加热到至少两个可选择性控制的温度区域; 确定相对于包括所述两个可选择性控制的温度区域的所述工艺表面的预定区域上的参考尺寸的蚀刻特征的第一尺寸变化; 确定所述两个可选择性控制的温度区域的操作温度，以实现所述第一尺寸变化中的目标尺寸变化变化以实现期望的第二维度变化; 将工艺表面等离子体蚀刻到所需的工作温度; 以及确定用于至少一个随后等离子体蚀刻工艺中的实际尺寸变化变化。

8. 发明授权

US07078351B2 Photoresist intensive patterning and processing 失效
标题翻译：光刻胶强化图案和加工
公开(公告)号：US07078351B2
公开(公告)日：2006-07-18
申请号：US10361875
申请日：2003-02-10
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/30604 , H01L21/3081 , H01L21/31116 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/76802
摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.
摘要翻译：首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

9. 发明授权

US07074727B2 Process for improving dielectric properties in low-k organosilicate dielectric material 失效
标题翻译：改进低k有机硅酸盐介电材料介电性能的方法
公开(公告)号：US07074727B2
公开(公告)日：2006-07-11
申请号：US10615628
申请日：2003-07-09
申请人： Peng-Fu Hsu , Jyu-Horng Shieh , Yung-Cheng Lu , Hun-Jan Tao , Yuan-Hung Chiu
发明人： Peng-Fu Hsu , Jyu-Horng Shieh , Yung-Cheng Lu , Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： C08G77/00 , H01L21/768
CPC分类号： C08G77/38
摘要： Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.
摘要翻译：低k有机硅酸盐电介质材料可以暴露于一系列试剂，包括卤化试剂，烷基化试剂和终止试剂，以反转由以前的处理步骤引起的介电性质的退化。

10. 发明授权

US06777340B1 Method of etching a silicon containing layer using multilayer masks 有权
标题翻译：使用多层掩模蚀刻含硅层的方法
公开(公告)号：US06777340B1
公开(公告)日：2004-08-17
申请号：US09949505
申请日：2001-09-10
申请人： Hsien-Kuang Chiu , Fang-Chang Chen , Hun-Jan Tao , Yuan-Hung Chiu , Jeng-Horng Chen
发明人： Hsien-Kuang Chiu , Fang-Chang Chen , Hun-Jan Tao , Yuan-Hung Chiu , Jeng-Horng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/32139
摘要： A new method is provided for the etch of ultra-small patterns in a silicon based surface. Under the first embodiment, a hardmask layer over a substrate and a layer of ARC over the hardmask layer are successively patterned. The patterned layer of ARC is removed, the remaining patterned hardmask layer is used as a mask for etching the substrate. Under the second embodiment, a first hardmask layer over a substrate, a second hardmask layer over the first hardmask layer and a layer of ARC over the second hardmask layer are successively patterned. The patterned layer of ARC and the second hardmask layer are removed, the remaining first patterned hardmask layer is used as a mask for etching the substrate.
摘要翻译：提供了一种用于在硅基表面中蚀刻超小图案的新方法。在第一实施例中，在衬底上的硬掩模层和硬掩模层上的ARC层被连续地图案化。去除图案化的ARC层，剩余的图案化硬掩模层用作蚀刻衬底的掩模。在第二实施例中，基板上的第一硬掩模层，第一硬掩模层上的第二硬掩模层和第二硬掩模层上的ARC层被连续地图案化。去除ARC和第二硬掩模层的图案层，剩余的第一图案化硬掩模层用作蚀刻衬底的掩模。

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