专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07512915B2 Embedded test circuit for testing integrated circuits at the die level 失效
标题翻译：嵌入式测试电路，用于在芯片级别测试集成电路
公开(公告)号：US07512915B2
公开(公告)日：2009-03-31
申请号：US11739819
申请日：2007-04-25
申请人： Darren Anand , Nazmul Habib , Robert McMahon , Troy Perry
发明人： Darren Anand , Nazmul Habib , Robert McMahon , Troy Perry
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , G06F2217/14 , H01L2924/0002 , H01L2924/00
摘要： A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.
摘要翻译：在机器可读介质中实例化的设计结构; 设计结构包括用于设计测试电路的所有必要信息。测试电路用于执行特定于设备的测试，并在集成电路（例如ASIC）上获取参数数据，使得每个芯片单独测试，而不需要过多的测试时间要求，附加的硅或特殊的测试设备。该设计结构包括至少一个测试电路，并且可以集成到IC设计中，以及用于产生最终设计结构的所有所需的制造数据。最终设计结构可以是GDS存储介质或适于将最终数据结构发送到例如制造商，代工厂，客户或其他设计公司的另一种形式的介质。

2. 发明申请

US20070033458A1 Diagnostic Method and Apparatus For Non-Destructively Observing Latch Data 失效
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US20070033458A1
公开(公告)日：2007-02-08
申请号：US11533907
申请日：2006-09-21
申请人： Darren Anand , John Goss , Peter Jacobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
发明人： Darren Anand , John Goss , Peter Jacobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
IPC分类号： G01R31/28
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递给控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

3. 发明申请

US20050120270A1 AUTOMATIC BIT FAIL MAPPING FOR EMBEDDED MEMORIES WITH CLOCK MULTIPLIERS 失效
标题翻译：具有时钟乘法器的嵌入式存储器的自动位失效映射
公开(公告)号：US20050120270A1
公开(公告)日：2005-06-02
申请号：US10707071
申请日：2003-11-19
申请人： Darren Anand , Kevin Gorman , Michael Nelms
发明人： Darren Anand , Kevin Gorman , Michael Nelms
IPC分类号： G06F11/00 , G11C29/00 , G11C29/14 , G11C29/56
CPC分类号： G11C29/56 , G11C29/14 , G11C29/56008 , G11C2029/5604
摘要： A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.
摘要翻译：位故障映射电路通过利用从低速自动测试设备（ATE）测试器产生的高速倍增时钟，精确地生成诸如DRAM的嵌入式存储器的位故障映射。该电路在ATE测试仪，被测嵌入式内存，内置自检（BIST）和内置冗余分析（BIRA）之间进行通信。通过在遇到失败时暂停BIST测试电路，即BIST预期数据与从阵列读取的实际数据之间的不匹配，然后移位位故障数据，提供嵌入式DRAM存储器的精确位故障映射使用低速ATE测试仪时钟关闭芯片。此后，通过使用高速内部时钟再次运行BIST，从故障点恢复高速测试，以提供高速位Fail Map。

4. 发明申请

US20090016129A1 DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD 有权
标题翻译：增加保险丝编程的设计结构
公开(公告)号：US20090016129A1
公开(公告)日：2009-01-15
申请号：US11775531
申请日：2007-07-10
申请人： Darren Anand , Michael Ouellette , Michael Ziegerhofer
发明人： Darren Anand , Michael Ouellette , Michael Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C17/165 , G11C29/027 , G11C29/802
摘要： A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.
摘要翻译：一种能够进行电子保险丝内存修复的设计结构。设计结构使用压缩比特串根据选择值生成另一个比特串。该选择值向编码逻辑元件提供指令，该编码逻辑元件产生第二位串。例如，选择值可以指示编码逻辑在压缩比特串中创建每个比特的重复副本以生成2n比特串。一旦使用第二位串编程熔丝，则将熔丝值作为第三串读出，其由解码逻辑元件根据选择值解码，从而改善存储器修复。

5. 发明申请

US20080030260A1 DESIGN STRUCTURE FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES 有权
标题翻译：改善电动可编程熔断器感应尺寸的设计结构
公开(公告)号：US20080030260A1
公开(公告)日：2008-02-07
申请号：US11872273
申请日：2007-10-15
申请人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
发明人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
IPC分类号： H01H37/76
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

6. 发明申请

US20080025071A1 METHOD FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES 有权
标题翻译：改善电动可编程熔丝感应尺寸的方法
公开(公告)号：US20080025071A1
公开(公告)日：2008-01-31
申请号：US11868046
申请日：2007-10-05
申请人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
发明人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
IPC分类号： G11C11/00
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.
摘要翻译：用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。

7. 发明申请

US20050104639A1 MODULAR DLL ARCHITECTURE FOR GENERATING MULTIPLE TIMINGS 失效
标题翻译：用于生成多个时间的模块化DLL体系结构
公开(公告)号：US20050104639A1
公开(公告)日：2005-05-19
申请号：US10707067
申请日：2003-11-19
申请人： Darren Anand , Kevin Gorman
发明人： Darren Anand , Kevin Gorman
IPC分类号： G06F1/04 , G11C7/22 , G11C11/407 , H03L7/00 , H03L7/06 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/07 , G11C7/22 , G11C7/222 , H03L7/0814
摘要： A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.
摘要翻译：一种能够产生多个多相时钟信号的模块化数字锁定环（DLL）架构，其特别适用于具有片上定时的嵌入式DRAM系统的同步。该架构包括单核频率锁定电路，其包括具有控制逻辑的延迟元件和能够将DLL系统时钟频率锁定到外部参考时钟的锁定电路，以及能够使多个内部时钟同步的多个次级锁相电路信号到外部参考时钟的任何相位。

8. 发明申请

US20050050415A1 METHOD FOR SEPARATING SHIFT AND SCAN PATHS ON SCAN-ONLY, SINGLE PORT LSSD LATCHES 失效
标题翻译：单独分离移位和扫描方法的方法LSSD LATCHES
公开(公告)号：US20050050415A1
公开(公告)日：2005-03-03
申请号：US10604908
申请日：2003-08-26
申请人： Darren Anand , John Barth , Steven Oakland , Michael Ouellette
发明人： Darren Anand , John Barth , Steven Oakland , Michael Ouellette
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.
摘要翻译：一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

9. 发明申请

US20050025277A1 DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA 失效
标题翻译：诊断方法和装置，用于非分析性观察数据
公开(公告)号：US20050025277A1
公开(公告)日：2005-02-03
申请号：US10604550
申请日：2003-07-30
申请人： Darren Anand , John Goss , Peter Jakobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
发明人： Darren Anand , John Goss , Peter Jakobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
IPC分类号： G11C19/00 , G11C29/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

10. 发明授权

US08028195B2 Structure for indicating status of an on-chip power supply system 有权
标题翻译：用于指示片上电源系统状态的结构
公开(公告)号：US08028195B2
公开(公告)日：2011-09-27
申请号：US12114070
申请日：2008-05-02
申请人： Darren Anand , John A. Fifield , Kevin W. Gorman
发明人： Darren Anand , John A. Fifield , Kevin W. Gorman
IPC分类号： G06F11/00
CPC分类号： G01R31/31721 , G06F17/505 , G06F2217/78
摘要： A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于指示具有多个电源的片上电源系统的状态的系统，具有用于接收数字符合性信号的电力系统状态寄存器，与多个电源中的一个并且具有相关联的合规级别，其中每个数字符合信号指示其相关联的电源是否在相关联的合规级别操作，并且其中电力系统状态寄存器基于数字信号产生电源状态信号指示数字符合信号状态的符合性信号; 以及用于输出电源状态信号的输出，其中如果电源正在其相关联的顺应性水平下操作，则电源状态信号指示电源正在通过，否则电源状态信号指示电源发生故障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式