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1. 发明申请

US20050013187A1 METHOD FOR REDUCED ELECTRICAL FUSING TIME 失效
标题翻译：降低电气熔融时间的方法
公开(公告)号：US20050013187A1
公开(公告)日：2005-01-20
申请号：US10604414
申请日：2003-07-18
申请人： Darren Anand , John Barth , Steven Oakland , Michael Ouellette
发明人： Darren Anand , John Barth , Steven Oakland , Michael Ouellette
IPC分类号： G11C17/00 , G11C17/16 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.
摘要翻译：一种用于减少使用冗余eFuse电路制造的半导体器件的测试时间的方法和电熔丝电路设计。除了保险丝锁存器和图案锁存器以及eFuse电路的其他逻辑元件之外，在每个eFuse电路上还提供两对一多路复用器（MUX）。保险丝图案锁存器中存储有要熔断保险丝的信息。由模式锁存器产生的输出与程序输入进行“与”运算以提供MUX的选择信号。基于选择信号，MUX允许移位的“1”转到下一个锁存器，或者旁路下一个锁存器或锁存在换档链中，这取决于下一个保险丝是否被熔断。因此，本发明不仅可以串联地转换器件内的每个熔丝锁存器，而且仅使与熔断器相关联的熔丝锁存器能够保持传输“1”到下一个eFuse电路的传输。

2. 发明申请

US20050050415A1 METHOD FOR SEPARATING SHIFT AND SCAN PATHS ON SCAN-ONLY, SINGLE PORT LSSD LATCHES 失效
标题翻译：单独分离移位和扫描方法的方法LSSD LATCHES
公开(公告)号：US20050050415A1
公开(公告)日：2005-03-03
申请号：US10604908
申请日：2003-08-26
申请人： Darren Anand , John Barth , Steven Oakland , Michael Ouellette
发明人： Darren Anand , John Barth , Steven Oakland , Michael Ouellette
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.
摘要翻译：一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

3. 发明申请

US20060239088A1 METHOD AND APPARATUS FOR INCREASING FUSE PROGRAMMING YIELD THROUGH PREFERRED USE OF DUPLICATE DATA 有权
标题翻译：通过优化使用重复数据来增加保险丝编程的方法和装置
公开(公告)号：US20060239088A1
公开(公告)日：2006-10-26
申请号：US10908033
申请日：2005-04-26
申请人： Darren Anand , Michael Ouellette , Michael Ziegerhofer
发明人： Darren Anand , Michael Ouellette , Michael Ziegerhofer
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C17/165 , G11C29/027 , G11C29/4401 , G11C29/72
摘要： Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.
摘要翻译：测试集成电路存储器以发现有缺陷的存储器元件。为了更换有缺陷的存储器元件，选择备用存储器元件，并且生成字符串以指示哪些备用件替换有缺陷存储器元件中的哪一个。字符串的位数取决于多少存储器元件有缺陷。尽管一定数量的存储器元件是有缺陷的，这确定了串比特的数目，然而，确定集成电路上编程的多个保险丝的响应是相对于二进制数的编号有多少个熔丝可用于编程字符串位。也就是说，如果比相对于字符串位数（优选的）更多的熔丝可用于某个阈值数，则多于阈值编号。如果没有，那么只有该阈值数量的保险丝被编程。

4. 发明申请

US20070033458A1 Diagnostic Method and Apparatus For Non-Destructively Observing Latch Data 失效
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US20070033458A1
公开(公告)日：2007-02-08
申请号：US11533907
申请日：2006-09-21
申请人： Darren Anand , John Goss , Peter Jacobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
发明人： Darren Anand , John Goss , Peter Jacobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
IPC分类号： G01R31/28
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递给控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

5. 发明申请

US20090016129A1 DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD 有权
标题翻译：增加保险丝编程的设计结构
公开(公告)号：US20090016129A1
公开(公告)日：2009-01-15
申请号：US11775531
申请日：2007-07-10
申请人： Darren Anand , Michael Ouellette , Michael Ziegerhofer
发明人： Darren Anand , Michael Ouellette , Michael Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C17/165 , G11C29/027 , G11C29/802
摘要： A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.
摘要翻译：一种能够进行电子保险丝内存修复的设计结构。设计结构使用压缩比特串根据选择值生成另一个比特串。该选择值向编码逻辑元件提供指令，该编码逻辑元件产生第二位串。例如，选择值可以指示编码逻辑在压缩比特串中创建每个比特的重复副本以生成2n比特串。一旦使用第二位串编程熔丝，则将熔丝值作为第三串读出，其由解码逻辑元件根据选择值解码，从而改善存储器修复。

6. 发明申请

US20050025277A1 DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA 失效
标题翻译：诊断方法和装置，用于非分析性观察数据
公开(公告)号：US20050025277A1
公开(公告)日：2005-02-03
申请号：US10604550
申请日：2003-07-30
申请人： Darren Anand , John Goss , Peter Jakobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
发明人： Darren Anand , John Goss , Peter Jakobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
IPC分类号： G11C19/00 , G11C29/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

7. 发明申请

US20050030065A1 SYSTEM AND METHOD FOR IMPLEMENTING SELF-TIMED DECODED DATA PATHS IN INTEGRATED CIRCUITS 有权
标题翻译：在一体化电路中实现自定义解码数据块的系统和方法
公开(公告)号：US20050030065A1
公开(公告)日：2005-02-10
申请号：US10604621
申请日：2003-08-05
申请人： Darren Anand , John Barth
发明人： Darren Anand , John Barth
IPC分类号： H03K19/00 , H03K19/096
CPC分类号： H03K19/0008
摘要： A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transmitted from said transmitting storage elements. Encoding logic is used for encoding the transmitted data from the transmitting storage elements, wherein the encoded transmitted data is coupled to a plurality of data lines. The encoding logic is further configured so as to result in only one of the plurality of data lines being activated during a given data transmission cycle.
摘要翻译：自定时数据传输系统包括由相应的多个发送存储元件发送的至少两个数据位定义的数据位组。相应的多个数据接收存储元件接收从所述发送存储元件发送的数据。编码逻辑用于对来自发送存储元件的发送数据进行编码，其中编码的发送数据耦合到多条数据线。编码逻辑被进一步配置为使得在给定的数据传输周期期间只有多条数据线中的一条被激活。

8. 发明申请

US20090153172A1 STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM 有权
标题翻译：表示片上电源系统状态的结构
公开(公告)号：US20090153172A1
公开(公告)日：2009-06-18
申请号：US12114070
申请日：2008-05-02
申请人： Darren Anand , John A. Fifield , Kevin W. Gorman
发明人： Darren Anand , John A. Fifield , Kevin W. Gorman
IPC分类号： G01R31/40 , G01R31/28
CPC分类号： G01R31/31721 , G06F17/505 , G06F2217/78
摘要： A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于指示具有多个电源的片上电源系统的状态的系统，具有用于接收数字符合性信号的电力系统状态寄存器，与多个电源中的一个并且具有相关联的合规级别，其中每个数字符合信号指示其相关联的电源是否在相关联的合规级别操作，并且其中电力系统状态寄存器基于数字信号产生电源状态信号指示数字符合信号状态的符合性信号; 以及用于输出电源状态信号的输出，其中如果电源正在其相关联的顺应性水平下操作，则电源状态信号指示电源正在通过，否则电源状态信号指示电源发生故障。

9. 发明申请

US20080270951A1 Embedded Test Circuit For Testing Integrated Circuits At The Die Level 失效
标题翻译：嵌入式测试电路，用于在模具级别测试集成电路
公开(公告)号：US20080270951A1
公开(公告)日：2008-10-30
申请号：US11739819
申请日：2007-04-25
申请人： Darren Anand , Nazmul Habib , Robert McMahon , Troy Perry
发明人： Darren Anand , Nazmul Habib , Robert McMahon , Troy Perry
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , G06F2217/14 , H01L2924/0002 , H01L2924/00
摘要： A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.
摘要翻译：在机器可读介质中实例化的设计结构; 设计结构包括用于设计测试电路的所有必要信息。测试电路用于执行特定于设备的测试，并在集成电路（例如ASIC）上获取参数数据，使得每个芯片单独测试，而不需要过多的测试时间要求，附加的硅或特殊的测试设备。该设计结构包括至少一个测试电路，并且可以集成到IC设计中，以及用于产生最终设计结构的所有所需的制造数据。最终设计结构可以是GDS存储介质或适于将最终数据结构发送到例如制造商，代工厂，客户或其他设计公司的另一种形式的介质。

10. 发明申请

US20050162799A1 FUSE LATCH WITH COMPENSATED PROGRAMMABLE RESISTIVE TRIP POINT 有权
标题翻译：具有可补偿可编程电阻点的保险丝锁定
公开(公告)号：US20050162799A1
公开(公告)日：2005-07-28
申请号：US10707963
申请日：2004-01-28
申请人： Darren Anand , John Fifield
发明人： Darren Anand , John Fifield
IPC分类号： G11C17/18 , H02H3/08
CPC分类号： G11C17/18
摘要： A fuse latch circuit with a current reference generator is described where the resistive switch point of the latch is stabilized against effects of manufacturing processing, operating voltage and temperature. A digital control word is used to select the desired resistive trip point of the fuse latch and compensation within the reference generator maintains this resistive trip point with high accuracy. The variable resistive trip point is set to a first value at test and then to a second value in use condition to enhance operating margin, and soft error immunity.
摘要翻译：描述了具有电流参考发生器的保险丝锁存电路，其中闩锁的电阻开关点对制造处理，工作电压和温度的影响是稳定的。使用数字控制字来选择熔丝锁存器的期望电阻跳变点，并且参考发生器内的补偿以高精度维持该电阻跳变点。可变电阻跳变点在测试时被设置为第一个值，然后在使用条件下设置为第二个值，以提高运算裕度和软误差抗扰度。

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