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1. 发明授权

US08095907B2 Reliability evaluation and system fail warning methods using on chip parametric monitors 有权
标题翻译：使用片上参数监视器的可靠性评估和系统故障预警方法
公开(公告)号：US08095907B2
公开(公告)日：2012-01-10
申请号：US11874950
申请日：2007-10-19
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/2894
摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
摘要翻译：使用片上参数监视器的可靠性评估和系统故障警告的方法。该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

2. 发明授权

US07917451B2 Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screens 有权
标题翻译：方法，设备和程序产品，以优化性能和泄漏屏幕的半导体产品产量预测
公开(公告)号：US07917451B2
公开(公告)日：2011-03-29
申请号：US12046237
申请日：2008-03-11
申请人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
发明人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
IPC分类号： G06F17/00
CPC分类号： G06F17/5036 , G06F17/5045 , G06F2217/14 , G06Q30/0283 , H01L22/20
摘要： An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.
摘要翻译：提供了一种装置，方法和程序产品来预测与性能屏幕或泄漏屏幕相关联的屈服损失。泄漏模型与片上测量相关。目前有限的产量是根据泄漏模型确定的。形成一个关于性能西格玛切割点与电路有限产量的数据库。基于从数据库中获取的性能西格玛切割点之一的电路限制产量引用了产品。报价与产品设计和测试有关。

3. 发明申请

US20100318313A1 MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效
标题翻译：统计应力的测量方法和阵列结构和可靠性结构测试
公开(公告)号：US20100318313A1
公开(公告)日：2010-12-16
申请号：US12482999
申请日：2009-06-11
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译：在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛。在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。

4. 发明授权

US07656182B2 Testing method using a scalable parametric measurement macro 失效
标题翻译：使用可扩展参数测量宏的测试方法
公开(公告)号：US07656182B2
公开(公告)日：2010-02-02
申请号：US11689150
申请日：2007-03-21
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert J. McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert J. McMahon
IPC分类号： G01R31/26
CPC分类号： G01R31/2894 , G01R31/2831 , G01R31/30
摘要： Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.
摘要翻译：公开了测试方法实施例，其中在后制造测试中，参数测量取自片上参数测量元件，并用于优化制造在线参数控制学习和/或优化产品筛选过程。具体来说，这些后期制造参数测量可用于配置芯片，而不会丢弃不合格的产品，而不会丢弃符合要求的产品，并且不需要高成本的功能测试。它们也可以用于识别来自设计的参数变化的产量敏感性，并且基于产量灵敏度为制造线改进提供反馈。此外，关于在制造和制造后水平上监测的关键参数的历史数据库可用于预测未来产量，从而预先改进生产线和/或更新供应链预测。

5. 发明申请

US20090251167A1 Array-Based Early Threshold Voltage Recovery Characterization Measurement 失效
标题翻译：基于阵列的早期阈值电压恢复特性测量
公开(公告)号：US20090251167A1
公开(公告)日：2009-10-08
申请号：US12061077
申请日：2008-04-02
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译：一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

6. 发明申请

US20090106712A1 RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS 有权
标题翻译：可靠性评估和系统故障警告使用芯片参数监视器的方法
公开(公告)号：US20090106712A1
公开(公告)日：2009-04-23
申请号：US11874950
申请日：2007-10-19
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/2894
摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
摘要翻译：使用片上参数监视器的可靠性评估和系统故障警告的方法。该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

7. 发明申请

US20090070722A1 METHOD FOR GENERATING DEVICE MODEL OVERRIDES THROUGH THE USE OF ON-CHIP PARAMETRIC MEASUREMENT MACROS 审中-公开
标题翻译：通过使用片上参数测量宏生成器件模型的方法
公开(公告)号：US20090070722A1
公开(公告)日：2009-03-12
申请号：US11851073
申请日：2007-09-06
申请人： Jeanne Bickford , John R. Gross , Nazmul Habib , Robert McMahon
发明人： Jeanne Bickford , John R. Gross , Nazmul Habib , Robert McMahon
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method generates area dependent design rules during semiconductor technology qualification by identifying the layout parametric variation in a semiconductor technology and establishing layout dependent design rules. This method applies the area dependent design rules to identify design sensitivity to area dependent design rules and to optimize semiconductor libraries and/or semiconductor products using an on-chip parametric monitor by designing processes for library elements, semiconductor design systems, and/or custom semiconductor products using the layout dependent design rules.
摘要翻译：一种方法通过识别半导体技术中的布局参数变化和建立依赖于布局的设计规则，在半导体技术鉴定期间产生区域相关设计规则。该方法应用区域依赖设计规则来识别对区域相关设计规则的设计灵敏度，并通过设计库单元，半导体设计系统和/或定制半导体的过程，使用片上参数监视器优化半导体库和/或半导体产品产品采用布局依赖设计规则。

8. 发明授权

US07382149B2 System for acquiring device parameters 有权
标题翻译：用于获取设备参数的系统
公开(公告)号：US07382149B2
公开(公告)日：2008-06-03
申请号：US11459367
申请日：2006-07-24
申请人： Darren L. Anand , Nazmul Habib , Robert J. McMahon , Troy J. Perry
发明人： Darren L. Anand , Nazmul Habib , Robert J. McMahon , Troy J. Perry
IPC分类号： G01R31/26
CPC分类号： G01R31/318511 , G01R31/31723 , G01R31/31724
摘要： A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.
摘要翻译：用于执行特定于设备的测试和获取定制集成电路（例如ASIC）的参数数据的系统，使得每个芯片被单独测试而没有过多的测试时间要求，附加的硅或特殊的测试设备。测试系统包括在ASIC设计中集成到未使用的回填空间中的器件测试结构，其测试与ASIC中的一些相同的一组虚设器件。器件测试结构包括用于指定测试类型和要激活的器件类型（例如pFET或nFET）的控制逻辑，用于在测试无效时保护SPM的保护电路，用于隔离被测器件（DUT）的隔离电路）和测试期间的任何漏电流的解码电路，以及用于向DUT提供测试输入（例如电压）的解码电路。通过控制要测试的设备和这些设备的电压条件，系统通过模具计算芯片上的线路的相对产品产量和健康状况。

9. 发明申请

US20130113514A1 SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL 有权
标题翻译：用于动态和自适应功率控制的速度波动
公开(公告)号：US20130113514A1
公开(公告)日：2013-05-09
申请号：US13288269
申请日：2011-11-03
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非易失性存储介质存储电压仓的边界作为速度分级测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

10. 发明授权

US08421495B1 Speed binning for dynamic and adaptive power control 有权
标题翻译：用于动态和自适应功率控制的速度分组
公开(公告)号：US08421495B1
公开(公告)日：2013-04-16
申请号：US13288269
申请日：2011-11-03
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： H03K19/003
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非易失性存储介质存储电压仓的边界作为速度分级测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

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