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1. 发明申请

US20070033458A1 Diagnostic Method and Apparatus For Non-Destructively Observing Latch Data 失效
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US20070033458A1
公开(公告)日：2007-02-08
申请号：US11533907
申请日：2006-09-21
申请人： Darren Anand , John Goss , Peter Jacobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
发明人： Darren Anand , John Goss , Peter Jacobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
IPC分类号： G01R31/28
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递给控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

2. 发明申请

US20050025277A1 DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA 失效
标题翻译：诊断方法和装置，用于非分析性观察数据
公开(公告)号：US20050025277A1
公开(公告)日：2005-02-03
申请号：US10604550
申请日：2003-07-30
申请人： Darren Anand , John Goss , Peter Jakobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
发明人： Darren Anand , John Goss , Peter Jakobsen , Michael Ouellette , Thomas Sopchak , Donald Wheater
IPC分类号： G11C19/00 , G11C29/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

3. 发明申请

US20060284174A1 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer 有权
标题翻译：用于在半导体晶片上并入的半导体芯片的测试装置
公开(公告)号：US20060284174A1
公开(公告)日：2006-12-21
申请号：US11477963
申请日：2006-06-28
申请人： Brion Keller , Bernd Koenemann , David Lackey , Donald Wheater
发明人： Brion Keller , Bernd Koenemann , David Lackey , Donald Wheater
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2889 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.
摘要翻译：将提供用于同时测试半导体晶片上的多个未切割芯片的多个通信路径的装置，其将同时允许每个这样的通信路径在使用最少数量的测试器接触的同时服务多于一个芯片。本发明的这些和其它目的，特征和优点在其上具有多个切口隔离的集成芯片的半导体晶片中实现，每个所述芯片通过两个不同的刺激总线耦合到策略放置的管理电路中的至少两个不同的管理电路 ; 每个芯片通过布置在芯片之间的切口区域中的选择控制电路耦合到每个管理电路。正是这种冗余可以显着降低相关管理或选择控制电路故障的可能性。刺激总线还可以用于为每个芯片提供并行串行扫描数据以及功率和其他信号，如时钟和使能和禁止信号。每个芯片控制电路为芯片提供电源，总线时钟，控制，使能和响应线路，还可以通过切口中的适当线路连接到每个芯片。

4. 发明申请

US20070204193A1 MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) 有权
标题翻译：用于逻辑内置自检的微控制器（LBIST）
公开(公告)号：US20070204193A1
公开(公告)日：2007-08-30
申请号：US11276413
申请日：2006-02-28
申请人： Gary Grise , David Lackey , Steven Oakland , Donald Wheater
发明人： Gary Grise , David Lackey , Steven Oakland , Donald Wheater
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.
摘要翻译：内置自检（BIST）微控制器集成电路，适用于逻辑验证。微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

5. 发明申请

US20050088888A1 Method for testing embedded DRAM arrays 失效
标题翻译：嵌入式DRAM阵列测试方法
公开(公告)号：US20050088888A1
公开(公告)日：2005-04-28
申请号：US10994496
申请日：2004-11-22
申请人： Laura Chadwick , William Corbin , Jeffrey Dreibelbis , Erik Nelson , Thomas Obremski , Toshiharu Saitoh , Donald Wheater
发明人： Laura Chadwick , William Corbin , Jeffrey Dreibelbis , Erik Nelson , Thomas Obremski , Toshiharu Saitoh , Donald Wheater
IPC分类号： G11C29/26 , G11C7/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
摘要翻译：一种用于测试由DRAM块组成的DRAM的方法和系统。该方法包括：在基于处理器的内置自检系统中，生成测试数据模式; 对于每个DRAM块，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及从DRAM块执行结果数据模式的读取; 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在所述DRAM块之后执行所得到的数据模式的读取在执行暂停预定时间段; 并且其中DRAM块的两个或更多个的预定时间段的暂停的至少一部分在时间上重叠。

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