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1. 发明申请

US20080253220A1 Flexible RAM Clock Enable 有权
标题翻译：灵活的RAM时钟使能
公开(公告)号：US20080253220A1
公开(公告)日：2008-10-16
申请号：US12145440
申请日：2008-06-24
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G11C8/18
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

2. 发明授权

US07397726B1 Flexible RAM clock enable 失效
标题翻译：灵活的RAM时钟使能
公开(公告)号：US07397726B1
公开(公告)日：2008-07-08
申请号：US11399771
申请日：2006-04-07
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。

3. 发明授权

US08271821B2 Flexible RAM clock enable 有权
标题翻译：灵活的RAM时钟使能
公开(公告)号：US08271821B2
公开(公告)日：2012-09-18
申请号：US12145440
申请日：2008-06-24
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

4. 发明授权

US06480028B2 Programmable logic device architectures with super-regions having logic regions and memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06480028B2
公开(公告)日：2002-11-12
申请号：US10062741
申请日：2002-02-01
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pederson , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pederson , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在更高长度的超超区域互连资源装置。

5. 发明授权

US06215326B1 Programmable logic device architecture with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06215326B1
公开(公告)日：2001-04-10
申请号：US09266235
申请日：1999-03-10
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

6. 发明授权

US5850152A Programmable logic array integrated circuit devices 失效
公开(公告)号：US5850152A
公开(公告)日：1998-12-15
申请号：US834998
申请日：1997-04-07
申请人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

7. 发明授权

US5850151A Programmable logic array intergrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US5850151A
公开(公告)日：1998-12-15
申请号：US834996
申请日：1997-04-07
申请人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David E. Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David W. Mendel , Craig S. Lytle , Robert R. N. Bielby , Kerry Veenstra
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

8. 发明授权

US06879183B2 Programmable logic device architectures with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06879183B2
公开(公告)日：2005-04-12
申请号：US10260712
申请日：2002-09-27
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

9. 发明授权

US5963069A System for distributing clocks using a delay lock loop in a programmable logic circuit 失效
标题翻译：用于在可编程逻辑电路中使用延迟锁定环路分配时钟的系统
公开(公告)号：US5963069A
公开(公告)日：1999-10-05
申请号：US971315
申请日：1997-11-17
申请人： David E. Jefferson , L. Todd Cope , Srinivas Reddy , Richard G. Cliff
发明人： David E. Jefferson , L. Todd Cope , Srinivas Reddy , Richard G. Cliff
IPC分类号： G06F1/10 , H03K19/177 , H03L7/081 , H03L7/087 , H03L7/08
CPC分类号： H03K19/1774 , G06F1/10 , H03K19/17732 , H03L7/0814 , H03L7/087
摘要： A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.
摘要翻译：一种用于将时钟信号分配给集成电路上的许多点的系统（100）。该系统包括使用具有特定数字电路的延迟锁定环来完成相位误差检测和延迟元件选择。在一个实施例中，使用两个触发器来检测相位误差。在另一个实施例中，使用宏（202）和微相位检测器（218），并且通过使用第一级中的移位寄存器（210）和在第二级中的计数器（220），两级执行延迟元件选择。本发明的另一个特征是将参考时钟或同步时钟分配到集成电路上的电路的不同部分的能力。提供可选择的多个时钟分配系统。

10. 发明授权

US07236411B1 Programmable memory access parameters 有权
标题翻译：可编程存储器访问参数
公开(公告)号：US07236411B1
公开(公告)日：2007-06-26
申请号：US11187356
申请日：2005-07-21
申请人： Rahul Saini , Changsong Zhang , David E. Jefferson
发明人： Rahul Saini , Changsong Zhang , David E. Jefferson
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G06F17/5054 , G11C7/222
摘要： A programmable device can configure memory access parameters to optimize the performance of one or more of its memory units. A memory unit includes one or more programmable delay units connected with clock, control and/or data signals. The configuration data of the programmable device specifies delay values for each programmable delay unit. A programmable delay unit includes at least two signal paths having different timing characteristics. A switching circuit controlled by configuration data is used to select one of the signal paths as the output of the programmable delay unit. Programmable delay units can be connected in series or in parallel to increase the number of possible delays and/or to specify timing parameters of portions of the memory unit in absolute or relative terms. Programmable delay units can be used to vary the timing characteristics of the memory unit and to control the voltage split used to read data.
摘要翻译：可编程设备可以配置存储器访问参数以优化其一个或多个存储器单元的性能。存储器单元包括与时钟，控制和/或数据信号连接的一个或多个可编程延迟单元。可编程设备的配置数据指定每个可编程延迟单元的延迟值。可编程延迟单元包括具有不同定时特性的至少两个信号路径。由配置数据控制的开关电路用于选择一个信号路径作为可编程延迟单元的输出。可编程延迟单元可以串联或并联连接以增加可能的延迟的数量和/或以绝对或相对的方式指定存储器单元的部分的定时参数。可编程延迟单元可用于改变存储器单元的定时特性并控制用于读取数据的电压分配。

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