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1. 发明授权

US08593174B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US08593174B1
公开(公告)日：2013-11-26
申请号：US13539007
申请日：2012-06-29
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

2. 发明授权

US08356019B1 Method and apparatus for utilizing patterns in data to reduce file size 有权
标题翻译：利用数据中的图案来减少文件大小的方法和装置
公开(公告)号：US08356019B1
公开(公告)日：2013-01-15
申请号：US10316371
申请日：2002-12-11
申请人： Bruce Pedersen , Jim Park , Peter Kazarian
发明人： Bruce Pedersen , Jim Park , Peter Kazarian
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/30595 , H03M7/3079 , H03M7/3088 , H03M7/707
摘要： A method for managing records in an object-oriented database is disclosed. Modified representations of data in fields of records is generated in response to patterns in the data. The modified representations of the data is compressed utilizing similarities in the modified representations of the data.
摘要翻译：公开了一种用于管理面向对象数据库中的记录的方法。响应于数据中的模式生成记录字段中数据的修改表示。使用数据的修改表示中的相似性来压缩数据的修改表示。

3. 发明授权

US08237465B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US08237465B1
公开(公告)日：2012-08-07
申请号：US13050732
申请日：2011-03-17
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

4. 发明授权

US07800401B1 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US07800401B1
公开(公告)日：2010-09-21
申请号：US11841727
申请日：2007-08-20
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

5. 发明授权

US07757189B1 Super duplicate register removal 有权
标题翻译：超级重复注册删除
公开(公告)号：US07757189B1
公开(公告)日：2010-07-13
申请号：US11489013
申请日：2006-07-18
申请人： Bruce Pedersen , Greg William Baeckler
发明人： Bruce Pedersen , Greg William Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Redundant elements of digital designs, including digital designs with registered feedback, are identified and removed. The nodes of a design are assigned initial labels. The design is analyzed by selecting nodes associated with each label and identifying any equivalent nodes or complementary nodes to the selected node. Nodes are equivalent if they perform the same or complementary functions on input nodes assigned to the same labels. The selected node and its equivalent node, if any, are reassigned to the same label. Two or more complementary nodes are modified so that they have the same output. This analysis is repeated until all of the labels and associated nodes have been analyzed and there are no labels and associated nodes in need of further analysis. Following this analysis, equivalent nodes in the digital design will share the same label and all but one node with each label can be removed.
摘要翻译：数字设计的冗余元素，包括具有注册反馈的数字设计，被识别和删除。设计的节点被分配初始标签。通过选择与每个标签相关联的节点并且将所选节点的任何等效节点或互补节点识别来分析设计。如果节点在分配给相同标签的输入节点上执行相同或互补的功能，则节点是相同的。所选节点及其等效节点（如果有的话）被重新分配给相同的标签。修改两个或多个互补节点，使其具有相同的输出。重复此分析，直到所有标签和相关节点都被分析，并且没有标签和相关节点需要进一步分析。经过分析，数字设计中的等效节点将共享相同的标签，除了一个节点之外，每个标签都可以被删除。

6. 发明申请

US20090289660A1 INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于可编程逻辑集成电路设备的互连和输入/输出资源
公开(公告)号：US20090289660A1
公开(公告)日：2009-11-26
申请号：US12356317
申请日：2009-01-20
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

7. 发明授权

US07368944B1 Organizations of logic modules in programmable logic devices 有权
标题翻译：可编程逻辑器件中逻辑模块的组织
公开(公告)号：US07368944B1
公开(公告)日：2008-05-06
申请号：US11649748
申请日：2007-01-03
申请人： Michael D. Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
发明人： Michael D. Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.
摘要翻译：在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。这种分组中的逻辑元素被划分为至少两个子组。提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用比对方。

8. 发明申请

US20080074143A1 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US20080074143A1
公开(公告)日：2008-03-27
申请号：US11888317
申请日：2007-07-30
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter Kazarian , Andrew Leaver , David Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter Kazarian , Andrew Leaver , David Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

9. 发明授权

US07348827B2 Apparatus and methods for adjusting performance of programmable logic devices 有权
标题翻译：用于调节可编程逻辑器件性能的装置和方法
公开(公告)号：US07348827B2
公开(公告)日：2008-03-25
申请号：US10848953
申请日：2004-05-19
申请人： Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： G05F3/02
CPC分类号： H03K19/1731 , G06F17/5054 , H03K19/00369 , H03K2217/0018
摘要： A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
摘要翻译：可编程逻辑器件（PLD）包括用于调整或设置一个或多个晶体管的体偏置的机构。 PLD包括体偏置发生器。体偏置发生器被配置为设置可编程逻辑器件内的一个或多个晶体管的体偏置。更具体地，体偏置发生器设置晶体管的体偏置，以便折衷晶体管的性能和功耗。

10. 发明授权

US07323902B2 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US07323902B2
公开(公告)日：2008-01-29
申请号：US11189549
申请日：2005-07-25
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy L. Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy L. Lee
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输入端的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

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