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1. 发明授权

US07884638B1 Techniques for providing calibrated on-chip termination impedance 有权
标题翻译：提供校准的片上终端阻抗的技术
公开(公告)号：US07884638B1
公开(公告)日：2011-02-08
申请号：US12236201
申请日：2008-09-23
申请人： Vikram Santurkar , Hyun Yi
发明人： Vikram Santurkar , Hyun Yi
IPC分类号： H03K17/16
CPC分类号： H03K17/005 , H03H11/28 , H03K17/16 , H03K17/165 , H03K17/6872 , H04L25/0278 , H04L25/0298
摘要： An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circuit compares a signal from the first terminal to first and second reference signals to generate a first calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the supply voltage and a second calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the low voltage. The OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.
摘要翻译：片上终端（OCT）校准电路包括耦合在第一端子和电源电压之间的一个或多个晶体管，耦合在第一端子和低电压之间的一个或多个晶体管，以及反馈环路电路。反馈回路电路将来自第一端子的信号与第一和第二参考信号进行比较，以产生控制耦合在第一端子和电源电压之间的一个或多个晶体管的导通状态的第一校准代码，以及控制导电耦合在第一端子和低电压之间的一个或多个晶体管的状态。 OCT校准电路使用第一个校准代码和第二个校准代码控制引脚上的片上终端阻抗。

2. 发明授权

US07161381B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US07161381B1
公开(公告)日：2007-01-09
申请号：US10787818
申请日：2004-02-25
申请人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
发明人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/1776
摘要： A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
摘要翻译：可编程逻辑器件（PLD）包括第一存储器块和至少第二存储器块，其中两个存储器块具有不同的存储器大小。

3. 发明申请

US20100225349A1 Techniques for Providing Calibrated On-Chip Termination Impedance 有权
标题翻译：提供校准片上终端阻抗的技术
公开(公告)号：US20100225349A1
公开(公告)日：2010-09-09
申请号：US12780917
申请日：2010-05-16
申请人： Vikram Santurkar , Hyun Yi
发明人： Vikram Santurkar , Hyun Yi
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278 , H04L25/0298
摘要： Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.
摘要翻译：提供了用于校准集成电路上的片上终端阻抗的技术。片上终止（OCT）校准电路产生校准代码，其选择性地控制并联耦合的一组晶体管的导通状态。 OCT校准电路选择使晶体管的阻抗接近匹配阻抗的校准码。所选的校准代码控制引脚上的片上终端阻抗。根据一些实施例，OCT校准电路将来自晶体管的信号与两个或更多个参考信号进行比较，以改进校准的片上终端阻抗的容差范围。根据其他实施例，OCT校准电路在通过控制信号接通附加晶体管之后，基于来自晶体管的信号来选择校准码。控制信号不用于控制片上终端阻抗。

4. 发明申请

US20080297193A1 Techniques for Providing Calibrated On-Chip Termination Impedance 有权
标题翻译：提供校准片上终端阻抗的技术
公开(公告)号：US20080297193A1
公开(公告)日：2008-12-04
申请号：US12190481
申请日：2008-08-12
申请人： Vikram Santurkar , Hyun Yi
发明人： Vikram Santurkar , Hyun Yi
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278 , H04L25/0298
摘要： Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.
摘要翻译：提供了用于校准集成电路上的片上终端阻抗的技术。片上终止（OCT）校准电路产生校准代码，其选择性地控制并联耦合的一组晶体管的导通状态。 OCT校准电路选择使晶体管的阻抗接近匹配阻抗的校准码。所选的校准代码控制引脚上的片上终端阻抗。根据一些实施例，OCT校准电路将来自晶体管的信号与两个或更多个参考信号进行比较，以改进校准的片上终端阻抗的容差范围。根据其他实施例，OCT校准电路在通过控制信号接通附加晶体管之后，基于来自晶体管的信号来选择校准码。控制信号不用于控制片上终端阻抗。

5. 发明授权

US07410293B1 Techniques for sensing temperature and automatic calibration on integrated circuits 有权
标题翻译：用于感测集成电路温度和自动校准的技术
公开(公告)号：US07410293B1
公开(公告)日：2008-08-12
申请号：US11383937
申请日：2006-05-17
申请人： Vikram Santurkar , Quyen Doan
发明人： Vikram Santurkar , Quyen Doan
IPC分类号： G01K7/00
CPC分类号： G01K7/015 , G01K15/00 , G01K2219/00
摘要： Techniques are provided for sensing the temperature of an integrated circuit (IC). A diode is provided on an IC. The voltage across the diode varies with the temperature of the IC. A feedback loop is coupled around the diode to monitor the voltage across the diode. The feedback loop contains a comparator and logic circuitry that outputs a digital code. The digital code varies in response to changes in the diode voltage. The value of the digital code can be used to determine the temperature on the IC. Techniques are also provided for automatically calibrating a temperature sensing circuit to compensate for inaccuracies caused by variations in process, temperature, and supply voltage. A calibration circuit is added to the feedback loop in the temperature sensor. The calibration circuit generates an offset code that is used to adjust the digital code to compensate for variations in temperature, process, and supply voltage.
摘要翻译：提供了用于感测集成电路（IC）的温度的技术。 IC上提供二极管。二极管上的电压随着IC的温度而变化。二极管耦合一个反馈回路以监测二极管两端的电压。反馈回路包含输出数字代码的比较器和逻辑电路。数字代码根据二极管电压的变化而变化。数字码的值可用于确定IC上的温度。还提供了用于自动校准温度检测电路以补偿由过程，温度和电源电压变化引起的不准确度的技术。校准电路加到温度传感器的反馈回路中。校准电路产生偏移代码，用于调整数字代码以补偿温度，过程和电源电压的变化。

6. 发明申请

US20080094105A1 PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL CONVERTERS 有权
标题翻译：可编程多个供电区域，具有开关门级电平转换器
公开(公告)号：US20080094105A1
公开(公告)日：2008-04-24
申请号：US11548206
申请日：2006-10-10
申请人： Vikram Santurkar , Ravi Thiruveedhula , Hyun Yi
发明人： Vikram Santurkar , Ravi Thiruveedhula , Hyun Yi
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03K19/094
摘要： A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.
摘要翻译：提供了一种电平转换架构，其适应在以相应电压电平工作的逻辑块之间行进的信号。该架构包括在逻辑块之间串联连接的通道。通过门的一个门提供可选择的栅极电压源。基于配置随机存取存储器（CRAM）设置从多个电压中选择可选择的栅极电压源。在一个实施例中，半锁存器连接到一个通过门。在该实施例中，半锁存器是反馈回路的一部分，以最小化逻辑块之一中的逻辑元件的功率泄漏。还提供了一种用于管理功率消耗并在集成电路的区域之间提供电压电平转换的方法。

7. 发明授权

US08004308B2 Techniques for providing calibrated on-chip termination impedance 有权
标题翻译：提供校准的片上终端阻抗的技术
公开(公告)号：US08004308B2
公开(公告)日：2011-08-23
申请号：US12780917
申请日：2010-05-16
申请人： Vikram Santurkar , Hyun Yi
发明人： Vikram Santurkar , Hyun Yi
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278 , H04L25/0298
摘要： Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.
摘要翻译：提供了用于校准集成电路上的片上终端阻抗的技术。片上终止（OCT）校准电路产生校准代码，其选择性地控制并联耦合的一组晶体管的导通状态。 OCT校准电路选择使晶体管的阻抗接近匹配阻抗的校准码。所选的校准代码控制引脚上的片上终端阻抗。根据一些实施例，OCT校准电路将来自晶体管的信号与两个或更多个参考信号进行比较，以改进校准的片上终端阻抗的容差范围。根据其他实施例，OCT校准电路在通过控制信号接通附加晶体管之后，基于来自晶体管的信号来选择校准码。控制信号不用于控制片上终端阻抗。

8. 发明授权

US07855574B2 Programmable multiple supply regions with switched pass gate level converters 有权
标题翻译：可编程多个供电区域，具有开关栅极电平转换器
公开(公告)号：US07855574B2
公开(公告)日：2010-12-21
申请号：US11548206
申请日：2006-10-10
申请人： Vikram Santurkar , Ravi Thiruveedhula , Hyun Yi
发明人： Vikram Santurkar , Ravi Thiruveedhula , Hyun Yi
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03K19/094
摘要： A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.
摘要翻译：提供了一种电平转换架构，其适应在以相应电压电平工作的逻辑块之间行进的信号。该架构包括在逻辑块之间串联连接的通道。通过门的一个门提供可选择的栅极电压源。基于配置随机存取存储器（CRAM）设置从多个电压中选择可选择的栅极电压源。在一个实施例中，半锁存器连接到一个通过门。在该实施例中，半锁存器是反馈回路的一部分，以最小化逻辑块之一中的逻辑元件的功率泄漏。还提供了一种用于管理功率消耗并在集成电路的区域之间提供电压电平转换的方法。

9. 发明授权

US07432734B2 Versatile logic element and logic array block 有权
公开(公告)号：US07432734B2
公开(公告)日：2008-10-07
申请号：US11743625
申请日：2007-05-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

10. 发明申请

US20080061818A1 Techniques For Providing Calibrated On-Chip Termination Impedance 有权
标题翻译：提供校准片上终端阻抗的技术
公开(公告)号：US20080061818A1
公开(公告)日：2008-03-13
申请号：US11466451
申请日：2006-08-22
申请人： Vikram Santurkar , Hyun Yi
发明人： Vikram Santurkar , Hyun Yi
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , H04L25/0278 , H04L25/0298
摘要： Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.
摘要翻译：提供了用于校准集成电路上的片上终端阻抗的技术。片上终止（OCT）校准电路产生校准代码，其选择性地控制并联耦合的一组晶体管的导通状态。 OCT校准电路选择使晶体管的阻抗接近匹配阻抗的校准码。所选的校准代码控制引脚上的片上终端阻抗。根据一些实施例，OCT校准电路将来自晶体管的信号与两个或更多个参考信号进行比较，以改进校准的片上终端阻抗的容差范围。根据其他实施例，OCT校准电路在通过控制信号接通附加晶体管之后，基于来自晶体管的信号来选择校准码。控制信号不用于控制片上终端阻抗。

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