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1. 发明授权

US08816326B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08816326B2
公开(公告)日：2014-08-26
申请号：US13497249
申请日：2011-11-25
申请人： Huaxiang Yin , Jun Luo , Chao Zhao , Honggang Liu , Dapeng Chen
发明人： Huaxiang Yin , Jun Luo , Chao Zhao , Honggang Liu , Dapeng Chen
IPC分类号： H01L29/78 , H01L29/66 , H01L29/778 , H01L29/08
CPC分类号： H01L29/66462 , H01L29/0895 , H01L29/7391 , H01L29/7785 , Y10S977/938
摘要： A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.
摘要翻译：一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

2. 发明申请

US20130105763A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130105763A1
公开(公告)日：2013-05-02
申请号：US13497249
申请日：2011-11-25
申请人： Huaxiang Yin , Jun Luo , Chao Zhao , Honggang Liu , Dapeng Chen
发明人： Huaxiang Yin , Jun Luo , Chao Zhao , Honggang Liu , Dapeng Chen
IPC分类号： H01L29/78 , H01L21/336 , B82Y99/00
CPC分类号： H01L29/66462 , H01L29/0895 , H01L29/7391 , H01L29/7785 , Y10S977/938
摘要： A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.
摘要翻译：一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

3. 发明申请

US20130240996A1 Semiconductor Device and Method of Manufacturing the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130240996A1
公开(公告)日：2013-09-19
申请号：US13520611
申请日：2012-04-11
申请人： Huaxiang Yin , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/66545 , H01L29/66606 , H01L29/7833
摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节工作功能准确。

4. 发明申请

US20130241004A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241004A1
公开(公告)日：2013-09-19
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是增强。

5. 发明授权

US08994119B2 Semiconductor device with gate stacks having stress and method of manufacturing the same 有权
标题翻译：具有应力的栅极堆叠的半导体器件及其制造方法
公开(公告)号：US08994119B2
公开(公告)日：2015-03-31
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/51 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也增强。

6. 发明申请

US20130267073A1 Method of Manufacturing Fin Field Effect Transistor 审中-公开
标题翻译：制造鳍场效应晶体管的方法
公开(公告)号：US20130267073A1
公开(公告)日：2013-10-10
申请号：US13577252
申请日：2012-06-07
申请人： Huaxiang Yin , Wei He , Huicai Zhong , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Wei He , Huicai Zhong , Chao Zhao , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823431 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention discloses a method of manufacturing a fin field effect transistor, which comprises the steps of forming a plurality of first fin structures on a substrate, which extend along a first direction parallel to the substrate; forming a plurality of second fin structures on a substrate, which extend along a second direction parallel to the substrate and the second direction intersecting with the first direction; selectively removing a part of the second fin structures to form a plurality of gate lines; and selectively removing a part of the first fin structures to form a plurality of substrate lines. In the method of manufacturing a fin field effect transistor according to the present invention, the gate lines and substrate lines are formed simultaneously by first making uniform silicon wing lines and gate wing lines using a limiting photolithography patternizing technique and then performing a centralized cutting of the corresponding specific regions, thereby increasing uniformity and reducing process difficulty and cost.
摘要翻译：本发明公开了一种制造鳍状场效应晶体管的方法，其特征在于包括以下步骤：沿着平行于衬底的第一方向延伸的衬底上形成多个第一鳍结构; 在基板上形成多个第二翅片结构，所述第二鳍结构沿着平行于所述基板的第二方向延伸并且所述第二方向与所述第一方向相交; 选择性地去除所述第二鳍结构的一部分以形成多个栅极线; 以及选择性地去除所述第一鳍结构的一部分以形成多条基片线。在根据本发明的鳍状场效应晶体管的制造方法中，通过首先使用限制光刻图案化技术首先制造均匀的硅翼线和栅翼线，然后进行集中切割，同时形成栅极线和衬底线相应的特定区域，从而增加均匀性，降低工艺难度和成本。

7. 发明授权

US09548387B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09548387B2
公开(公告)日：2017-01-17
申请号：US13812941
申请日：2012-08-27
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L27/088 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L29/66818 , H01L29/7845 , H01L29/785
摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.
摘要翻译：本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

8. 发明授权

US08703617B2 Method for planarizing interlayer dielectric layer 有权
标题翻译：平面化层间电介质层的方法
公开(公告)号：US08703617B2
公开(公告)日：2014-04-22
申请号：US13147044
申请日：2011-02-17
申请人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
IPC分类号： H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/76819 , H01L21/31055 , H01L21/31116
摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.
摘要翻译：本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

9. 发明授权

US08664119B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08664119B2
公开(公告)日：2014-03-04
申请号：US13497526
申请日：2011-11-28
申请人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Lingkuan Meng , Dapeng Chen
IPC分类号： H01L21/311 , H01L21/461
CPC分类号： H01L21/31053 , H01L21/28079 , H01L21/28088 , H01L21/31055 , H01L21/31116 , H01L21/823807 , H01L29/66545
摘要： A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.
摘要翻译：一种半导体器件制造方法，包括：提供半导体衬底，在所述半导体衬底上设置栅极导体层以及位于所述栅极导体层两侧的源极区域和漏极区域，在所述半导体衬底上形成蚀刻停止层在蚀刻停止层上形成LTO层，化学机械抛光LTO层，在抛光的LTO层上形成SOG层，形成前金属绝缘层的蚀刻停止层，LTO层和SOG层，背面蚀刻SOG层和前金属绝缘层的蚀刻停止层，以露出栅极导体层，以及去除栅极导体层。

10. 发明授权

US08652893B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08652893B2
公开(公告)日：2014-02-18
申请号：US13510439
申请日：2011-11-25
申请人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.
摘要翻译：一种半导体器件及其制造方法，其中NMOS器件由通过PECVD具有高紫外光吸收系数的氮化硅膜覆盖，所述氮化硅膜在被受激光激光表面退火时可以很好地吸收紫外光，因此为了达到良好的脱氢效果，脱氢后，氮化硅膜具有较高的拉伸应力; 由于氮化硅膜具有高的紫外光吸收系数，因此不需要加热基板，从而避免了由于将基板加热脱氢而导致的对器件的不利影响，并且保持了由PECVD工艺引起的热量预算。

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