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1. 发明授权

US08607104B2 Memory diagnostics system and method with hardware-based read/write patterns 有权
标题翻译：内存诊断系统和基于硬件读/写模式的方法
公开(公告)号：US08607104B2
公开(公告)日：2013-12-10
申请号：US12972977
申请日：2010-12-20
申请人： Hanwoo Cho , Tahsin Askar , Philip E. Madrid , Guhan Krishnan , Brian W. Amick , Shawn Searles , Ryan J. Hensley
发明人： Hanwoo Cho , Tahsin Askar , Philip E. Madrid , Guhan Krishnan , Brian W. Amick , Shawn Searles , Ryan J. Hensley
IPC分类号： G06F11/00
CPC分类号： G11C29/1201 , G11C29/022
摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.
摘要翻译：一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。测试控制逻辑被配置为在连续命令之间产生间隙。配置环回连接将写入数据从写入路径路由到读取路径。数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成地址/命令环回状态输出。

2. 发明授权

US07263628B2 Method and apparatus for receiver circuit tuning 有权
标题翻译：接收机电路调谐方法和装置
公开(公告)号：US07263628B2
公开(公告)日：2007-08-28
申请号：US10378295
申请日：2003-03-03
申请人： Claude R. Gauthier , Aninda K. Roy , Pradeep R. Trivedi , Brian W. Amick
发明人： Claude R. Gauthier , Aninda K. Roy , Pradeep R. Trivedi , Brian W. Amick
IPC分类号： H04L7/00
CPC分类号： H03L7/081 , G06F1/12 , H03L7/18
摘要： A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.
摘要翻译：方法和装置通过收发器电路来调整传播延迟。发送装置被配置为产生控制信号，其中驱动电路的阻抗取决于控制信号。偏置发生器可操作地连接到发送装置，并且取决于控制信号。接收器电路可操作地连接到偏置发生器，其中偏置发生器布置成可操作地调节通过接收器电路的传播延迟。

3. 发明授权

US07110461B2 Technique to enlarge data eyes in wireline communication systems 有权
标题翻译：有线通信系统中扩大数据眼的技术
公开(公告)号：US07110461B2
公开(公告)日：2006-09-19
申请号：US10198459
申请日：2002-07-18
申请人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
发明人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
IPC分类号： H04L27/00
CPC分类号： H04L25/03828 , H04L25/4906
摘要： A method and apparatus for enlarging data eyes in a wireline communication system involves pre-coding a data signal before transmission to generate a constant frequency characteristic independent of a state of the pre-coded data signal. The receiving circuit includes a circuit that temporally expands at least a portion of the pre-coded data signal. The portion of the temporally expanded data signal is latched by the receiving circuit.
摘要翻译：用于在有线通信系统中放大数据眼睛的方法和装置包括在传输之前对数据信号进行预编码以产生与预编码数据信号的状态无关的恒定频率特性。接收电路包括暂时扩展预编码数据信号的至少一部分的电路。时间上扩展的数据信号的部分被接收电路锁存。

4. 发明授权

US07109767B1 Generating different delay ratios for a strobe delay 有权
标题翻译：为选通延迟生成不同的延迟比
公开(公告)号：US07109767B1
公开(公告)日：2006-09-19
申请号：US10889610
申请日：2004-07-12
申请人： Brian W. Amick , Aparna Ramachandran , Dong J. Yoon , Tri K. Tran , Gajendra P. Singh , Claude R. Gauthier
发明人： Brian W. Amick , Aparna Ramachandran , Dong J. Yoon , Tri K. Tran , Gajendra P. Singh , Claude R. Gauthier
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/085
摘要： A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.
摘要翻译：与典型的寄存器控制的延迟锁定环（RDLL）相比，已经发现数字延迟锁定环路具有减小的面积，用于控制对驱动异步FIFO的选通信号提供延迟的选通延迟线。该结果通过减少RDLL的比率计算（即齿轮逻辑）电路来实现。主延迟线接收一个控制码，将参考时钟延迟一个时钟周期。从属延迟线接收控制码，以将选通信号延迟预定分钟的时钟周期。主延迟线可以包括响应于控制代码的各个部分，其有效地将信号延迟了时钟周期的一部分，该延迟具有与从属延迟线的各个部分相关联的延迟的固定关系。

5. 发明授权

US07062662B2 I/O resonance cancellation circuit based on charge-pumped capacitors 有权
标题翻译：基于电荷泵浦电容器的I / O共振消除电路
公开(公告)号：US07062662B2
公开(公告)日：2006-06-13
申请号：US10328069
申请日：2002-12-23
申请人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
发明人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
IPC分类号： G06F1/26 , H02J1/02 , G05F3/02
CPC分类号： G06F1/26 , H02M1/15 , H02M3/07
摘要： An apparatus for canceling an effect of power supply resonance is provided. The effect of power supply resonance is a variation in power supply voltage potential. This variation may substantially affect an output buffer by causing the output buffer's output to sag below desired values. A voltage regulating circuit is coupled to power supply lines local to the output buffer where the voltage regulating circuit is most effective in reducing voltage potential variation. An exemplary voltage regulating circuit is provided that uses charge-pumped capacitors to raise the power supply voltage potential when it falls below a desired value. A second example of a voltage regulating circuit uses charge-pumped capacitors to lower the power supply voltage potential when it rises above a desired value.
摘要翻译：提供一种消除电源谐振效应的装置。电源谐振的影响是电源电压电位的变化。该变化可能通过使输出缓冲器的输出下降到期望值以下而基本上影响输出缓冲器。电压调节电路耦合到输出缓冲器本地的电源线，其中电压调节电路在降低电压电位变化方面是最有效的。提供了一种示例性的电压调节电路，其使用电荷泵电容器来降低电源电压下降到期望值以下的电压。电压调节电路的第二示例使用电荷泵电容器，当其上升到期望值以上时降低电源电压电位。

6. 发明授权

US07043379B2 Method for quantifying I/O chip/package resonance 有权
标题翻译：量化I / O芯片/封装谐振的方法
公开(公告)号：US07043379B2
公开(公告)日：2006-05-09
申请号：US10277302
申请日：2002-10-22
申请人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
发明人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
IPC分类号： G06F19/00
CPC分类号： G01R31/31924 , G01R31/31932 , H04L1/242
摘要： A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.
摘要翻译：提供了一种用于量化集成电路配电网络中谐振效应的方法。配电网络包括向集成电路提供电力的第一电源线和第二电源线。选择两个测试参数的测试范围，接收机的参考电压电位和集成电路的数据传输频率。在两个测试参数的每个组合中，位模式由集成电路传输到接收器。在发送的比特和接收的比特之间进行比较，以确定发送的比特是否被正确地接收。比较可以用于确定和报告允许正确接收发送位的参考电压电位和数据传输频率的值的范围。

7. 发明授权

US06788045B2 Method and apparatus for calibrating a delay locked loop charge pump current 有权
标题翻译：用于校准延迟锁定环电荷泵电流的方法和装置
公开(公告)号：US06788045B2
公开(公告)日：2004-09-07
申请号：US10147594
申请日：2002-05-17
申请人： Claude R. Gauthier , Brian W. Amick , Pradeep Trivedi , Dean Liu
发明人： Claude R. Gauthier , Brian W. Amick , Pradeep Trivedi , Dean Liu
IPC分类号： G01R2312
CPC分类号： H03L7/0812 , H03L7/0896
摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.
摘要翻译：提供了一种用于后期制造控制延迟锁定环电荷泵电流的校准和调整系统。校准和调节系统包括改变电荷泵电流量的调节装置。在延迟锁定环路中对电荷泵电流的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。可以存储并随后读取电荷泵电流期望的调节量的代表值来调整延迟锁定环路。

8. 发明授权

US08373447B2 Method and apparatus of alternating service modes of an SOI process circuit 有权
标题翻译： SOI工艺电路交替工作模式的方法和装置
公开(公告)号：US08373447B2
公开(公告)日：2013-02-12
申请号：US12953593
申请日：2010-11-24
申请人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
发明人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
IPC分类号： H03K17/00 , G06F1/08
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.
摘要翻译：一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

9. 发明申请

US20120159271A1 MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE PATTERNS 有权
标题翻译：存储器诊断系统和基于硬件的读/写模式的方法
公开(公告)号：US20120159271A1
公开(公告)日：2012-06-21
申请号：US12972977
申请日：2010-12-20
申请人： Hanwoo Cho , Tahsin Askar , Philip E. Madrid , Guhan Krishnan , Brian W. Amick , Shawn Searles , Ryan J. Hensley
发明人： Hanwoo Cho , Tahsin Askar , Philip E. Madrid , Guhan Krishnan , Brian W. Amick , Shawn Searles , Ryan J. Hensley
IPC分类号： G06F11/263
CPC分类号： G11C29/1201 , G11C29/022
摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.
摘要翻译：一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。测试控制逻辑被配置为在连续命令之间产生间隙。配置环回连接将写入数据从写入路径路由到读取路径。数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成地址/命令环回状态输出。

10. 发明申请

US20120126871A1 METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT 有权
标题翻译： SOI工艺电路替代服务模式的方法与装置
公开(公告)号：US20120126871A1
公开(公告)日：2012-05-24
申请号：US12953593
申请日：2010-11-24
申请人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
发明人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
IPC分类号： G06F1/04
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.
摘要翻译：一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

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