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1. 发明授权

US07263628B2 Method and apparatus for receiver circuit tuning 有权
标题翻译：接收机电路调谐方法和装置
公开(公告)号：US07263628B2
公开(公告)日：2007-08-28
申请号：US10378295
申请日：2003-03-03
申请人： Claude R. Gauthier , Aninda K. Roy , Pradeep R. Trivedi , Brian W. Amick
发明人： Claude R. Gauthier , Aninda K. Roy , Pradeep R. Trivedi , Brian W. Amick
IPC分类号： H04L7/00
CPC分类号： H03L7/081 , G06F1/12 , H03L7/18
摘要： A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.
摘要翻译：方法和装置通过收发器电路来调整传播延迟。发送装置被配置为产生控制信号，其中驱动电路的阻抗取决于控制信号。偏置发生器可操作地连接到发送装置，并且取决于控制信号。接收器电路可操作地连接到偏置发生器，其中偏置发生器布置成可操作地调节通过接收器电路的传播延迟。

2. 发明授权

US06573770B1 Programmable leakage current offset for delay locked loop 有权
标题翻译：用于延迟锁定环路的可编程漏电流补偿
公开(公告)号：US06573770B1
公开(公告)日：2003-06-03
申请号：US10230726
申请日：2002-08-29
申请人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick , Dean Liu
发明人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick , Dean Liu
IPC分类号： H03L706
CPC分类号： H03L7/0812 , H03L7/0891
摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.
摘要翻译：提供了延迟锁定环路漏电流的制造后调整方法和装置。调整系统包括调整电路，调整漏电流补偿电路以补偿延迟锁定环中的电容器的漏电流。电容器连接到延迟锁定环路的控制电压。在延迟锁定环路中的这种对漏电流的控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。

3. 发明授权

US06570421B1 Programmable leakage current offset for phase locked loop 有权
标题翻译：用于锁相环的可编程泄漏电流偏移
公开(公告)号：US06570421B1
公开(公告)日：2003-05-27
申请号：US10230862
申请日：2002-08-29
申请人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick
发明人： Claude R. Gauthier , Pradeep R. Trivedi , Brian W. Amick
IPC分类号： H03L706
CPC分类号： H03L7/0893 , H03L7/18
摘要： A method and apparatus for post-fabrication adjustment of a phase locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the phase locked loop. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated.
摘要翻译：提供了一种用于制造后调整锁相环漏电流的方法和装置。调整系统包括调整电路，调整漏电流补偿电路以补偿锁相环中的电容器的漏电流。电容器连接到锁相环的控制电压。在锁相环中的泄漏电流的这种控制允许设计者在制造了锁相环之后实现期望的锁相环工作特性。

4. 发明授权

US06618277B2 Apparatus for reducing the supply noise near large clock drivers 有权
公开(公告)号：US06618277B2
公开(公告)日：2003-09-09
申请号：US09930537
申请日：2001-08-14
申请人： Claude R. Gauthier , Brian W. Amick , Tyler J. Thorp , Pradeep R. Trivedi , Dean Liu
发明人： Claude R. Gauthier , Brian W. Amick , Tyler J. Thorp , Pradeep R. Trivedi , Dean Liu
IPC分类号： H02M700
CPC分类号： H02M1/12 , G06F1/04 , G06F1/26 , H02M1/10
摘要： An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.

5. 发明授权

US06476663B1 Method for reducing supply noise near an on-die thermal sensor 有权
标题翻译：降低管芯热传感器附近供电噪声的方法
公开(公告)号：US06476663B1
公开(公告)日：2002-11-05
申请号：US09929151
申请日：2001-08-14
申请人： Claude R. Gauthier , Brian W. Amick , Tyler J. Thorp , Dean Liu , Pradeep R. Trivedi
发明人： Claude R. Gauthier , Brian W. Amick , Tyler J. Thorp , Dean Liu , Pradeep R. Trivedi
IPC分类号： H01L3500
CPC分类号： G01K7/00 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing power supply noise in the power supply system of a thermal sensor has been developed. The method includes powering up a thermal sensor and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the thermal sensor.
摘要翻译：已经开发了用于降低热传感器的电源系统中的电源噪声的方法。该方法包括加热热传感器并在电源端子上插入分流电阻。分流电阻与热传感器并联插入。

6. 发明授权

US06501328B1 Method for reducing peak to peak jitter in a dual-loop delay locked loop 有权
标题翻译：降低双回路延迟锁定环路峰峰值抖动的方法
公开(公告)号：US06501328B1
公开(公告)日：2002-12-31
申请号：US09930435
申请日：2001-08-14
申请人： Claude R. Gauthier , Brian W. Amick , Tyler J. Thorp , Dean Liu , Pradeep R. Trivedi
发明人： Claude R. Gauthier , Brian W. Amick , Tyler J. Thorp , Dean Liu , Pradeep R. Trivedi
IPC分类号： H03B100
CPC分类号： H03L7/0812
摘要： A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.
摘要翻译：已经开发了用于减小延迟锁定环路的电源系统中的电源噪声的方法。该方法包括上电延迟锁定环路，并在电源端子上插入分流电阻。分流电阻与延迟锁定环并联插入。

7. 发明授权

US06829548B2 DLL static phase error measurement technique 有权
标题翻译： DLL静态相位误差测量技术
公开(公告)号：US06829548B2
公开(公告)日：2004-12-07
申请号：US10406541
申请日：2003-04-03
申请人： Priya Ananthanarayanan , Pradeep R. Trivedi , Claude R. Gauthier
发明人： Priya Ananthanarayanan , Pradeep R. Trivedi , Claude R. Gauthier
IPC分类号： G06F1100
CPC分类号： H03L7/0812 , G01R25/005
摘要： An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.
摘要翻译：用于测量延迟锁定环路中的静态相位误差的装置包括第一测试阶段和第二测试阶段。第一测试阶段接收参考时钟，芯片时钟和控制信号。与第一测试级并行，第二测试级接收参考时钟，芯片时钟和控制信号的补码。根据控制信号，第一测试级输出第一测试信号，并且根据控制信号的补码，第二测试级输出第二测试信号。第一测试信号和第二测试信号用于根据控制信号和控制信号的补码产生一组静态相位误差测量值。通过对静态相位误差测量值进行平均，对延迟锁定环路测量静态相位误差。

8. 发明授权

US06686785B2 Deskewing global clock skew using localized DLLs 有权
标题翻译：使用本地化DLL来消除全局时钟偏移
公开(公告)号：US06686785B2
公开(公告)日：2004-02-03
申请号：US09975359
申请日：2001-10-11
申请人： Dean Liu , Tyler J. Thorp , Pradeep R. Trivedi , Gin S. Yee , Claude R. Gauthier
发明人： Dean Liu , Tyler J. Thorp , Pradeep R. Trivedi , Gin S. Yee , Claude R. Gauthier
IPC分类号： H03L706
CPC分类号： H03L7/07 , G06F1/10 , H03L7/0814
摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.
摘要翻译：集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分。到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。集成电路上的这种布置导致时钟网格偏移减少。

9. 发明授权

US06570423B1 Programmable current source adjustment of leakage current for phase locked loop 有权
标题翻译：锁相环漏电流可编程电流源调节
公开(公告)号：US06570423B1
公开(公告)日：2003-05-27
申请号：US10230596
申请日：2002-08-29
申请人： Pradeep R. Trivedi , Claude R. Gauthier , Sudhakar Bobba
发明人： Pradeep R. Trivedi , Claude R. Gauthier , Sudhakar Bobba
IPC分类号： H03L706
CPC分类号： H03L7/0893 , H03L7/18
摘要： A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.
摘要翻译：提供了一种用于相位锁定环路漏电流的制造后调整的方法和装置。调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。电容器连接到锁相环的控制电压。可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。可编程电流源由组合逻辑电路选择性地调节。对相位锁定环中的漏电流的这种控制允许设计者在制造可调锁相环之后实现期望的锁相环工作特性。

10. 发明授权

US06570420B1 Programmable current source adjustment of leakage current for delay locked loop 有权
标题翻译：用于延迟锁定环路的可编程电流源调节漏电流
公开(公告)号：US06570420B1
公开(公告)日：2003-05-27
申请号：US10230649
申请日：2002-08-29
申请人： Pradeep R. Trivedi , Claude R. Gauthier , Dean Liu
发明人： Pradeep R. Trivedi , Claude R. Gauthier , Dean Liu
IPC分类号： H03L706
CPC分类号： H03L7/0891 , H03L7/0812
摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.
摘要翻译：提供了延迟锁定环路漏电流的制造后调整方法和装置。调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。电容器连接到延迟锁定环路的控制电压。可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。可编程电流源由组合逻辑电路选择性地调节。对延迟锁定环路中的漏电流的这种控制允许设计者在制造可调延迟锁定环路之后实现期望的延迟锁定环路工作特性。

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