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1. 发明授权

US07109767B1 Generating different delay ratios for a strobe delay 有权
标题翻译：为选通延迟生成不同的延迟比
公开(公告)号：US07109767B1
公开(公告)日：2006-09-19
申请号：US10889610
申请日：2004-07-12
申请人： Brian W. Amick , Aparna Ramachandran , Dong J. Yoon , Tri K. Tran , Gajendra P. Singh , Claude R. Gauthier
发明人： Brian W. Amick , Aparna Ramachandran , Dong J. Yoon , Tri K. Tran , Gajendra P. Singh , Claude R. Gauthier
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/085
摘要： A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.
摘要翻译：与典型的寄存器控制的延迟锁定环（RDLL）相比，已经发现数字延迟锁定环路具有减小的面积，用于控制对驱动异步FIFO的选通信号提供延迟的选通延迟线。该结果通过减少RDLL的比率计算（即齿轮逻辑）电路来实现。主延迟线接收一个控制码，将参考时钟延迟一个时钟周期。从属延迟线接收控制码，以将选通信号延迟预定分钟的时钟周期。主延迟线可以包括响应于控制代码的各个部分，其有效地将信号延迟了时钟周期的一部分，该延迟具有与从属延迟线的各个部分相关联的延迟的固定关系。

2. 发明申请

US20160341668A1 ANGLED CONFOCAL SPECTROSCOPY 审中-公开
公开(公告)号：US20160341668A1
公开(公告)日：2016-11-24
申请号：US15111894
申请日：2015-01-15
申请人： Raj Gupta , Steven Francis Nagle , Gajendra P. Singh , Owen R. Falk
发明人： Raj Gupta , Steven Francis Nagle , Gajendra P. Singh , Owen R. Falk
IPC分类号： G01N21/65 , G01J3/02 , G01J3/44
CPC分类号： G01N21/65 , G01J3/0202 , G01J3/0208 , G01J3/0237 , G01J3/0262 , G01J3/44 , G01N21/4795 , G01N21/6458
摘要： Disclosed herein are systems and methods for performing angled confocal spectroscopy. Angled confocal spectroscopy permits sensitive, non-invasive investigation of numerous analytes in a wide variety of samples, including tissues and bodily fluids. The methods and systems disclosed herein can be used to measure spectroscopic signatures of analytes within well-defined and very small regions of samples, while at the same time achieving superior rejection of signal contributions from analytes within the sample that do not fall within a volume of interest. Accordingly, measurements can be performed at comparatively high signal-to-noise ratios, and can provide information such as concentrations and distributions of sample analytes at high spatial resolution. By using cylindrically-focused illumination light, samples can be excited by a “sheet” of light, allowing spatial signal averaging and enhancing the stability and reproducibility of the measurements.
摘要翻译：本文公开了用于进行角度共焦光谱的系统和方法。角度共焦光谱法允许对各种样品（包括组织和体液）中的许多分析物进行敏感，非侵入性的研究。本文公开的方法和系统可用于测量在定义良好且非常小的样品区域内的分析物的光谱特征，同时从样品内的分析物的信号贡献优先排除不属于利益。因此，可以在相对高的信噪比下进行测量，并且可以以高空间分辨率提供诸如样品分析物的浓度和分布的信息。通过使用圆柱聚焦的照明光，可以通过“片”光来激发样品，从而允许空间信号平均并增强测量的稳定性和再现性。

3. 发明授权

US06420903B1 High speed multiple-bit flip-flop 有权
标题翻译：高速多位触发器
公开(公告)号：US06420903B1
公开(公告)日：2002-07-16
申请号：US09638338
申请日：2000-08-14
申请人： Gajendra P. Singh , Joseph I. Chamdani , Renu Raman
发明人： Gajendra P. Singh , Joseph I. Chamdani , Renu Raman
IPC分类号： H03K1900
CPC分类号： G06F9/3851 , G06F9/3869
摘要： A vertical multi-threading processor includes one or more execution pipelines that are formed from a plurality of multiple-bit pipeline register flip-flops. The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage.
摘要翻译：垂直多线程处理器包括由多个多位流水线寄存器触发器形成的一个或多个执行流水线。多位流水线寄存器触发器提供多个存储位。多位流水线寄存器触发器的各个比特存储相应多个线程或进程之一的数据。当执行（第一）过程由于失速条件（例如高速缓存未命中）而停止时，多位寄存器触发器的活动位被停止，从流水线上的活动中移除，并且先前不活动的位变为活动执行以前无效（第二）过程。在每个流水线阶段，停止的第一进程的所有状态都保存在单个多位寄存器触发器的暂时不活动位中。

4. 发明授权

US07120915B1 Thread switch circuit design and signal encoding for vertical threading 有权
标题翻译：线程开关电路设计和垂直线程信号编码
公开(公告)号：US07120915B1
公开(公告)日：2006-10-10
申请号：US09716545
申请日：2000-11-20
申请人： Gajendra P. Singh , Joseph I. Chamdani , Renu Raman , Rabin A. Sugumar
发明人： Gajendra P. Singh , Joseph I. Chamdani , Renu Raman , Rabin A. Sugumar
IPC分类号： G06F9/46 , G06F9/40 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/3869
摘要： A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal. The apparatus further provides means for generating intermediary signals within a control block and then generating output signals to a data storage block. The apparatus also involves generating timing signals to a plurality of flip-flops dependent upon the behavior of the multi-function signal.
摘要翻译：已经开发了用于在微处理器中实现垂直多线程而不在处理器中实现附加信号线的方法和装置。该方法使用预先存在的信号作为多功能信号，使得多功能信号可用于时钟使能，时钟禁止和扫描使能功能。单个多功能信号根据触发器的需要显示多种功能，以在多种模式下工作。该方法允许使用预先存在的信号线作为处理线程切换信号，否则在不存在多功能信号的情况下，该信号线将不得不被明确地硬接线。该方法还包括允许将多位触发器放置在流水线中的连续阶段，以便于垂直多线程，并且实际上增加处理器性能。该装置提供用于区分由多功能信号表现的特定特征的装置。该装置还提供用于在控制块内产生中间信号，然后产生到数据存储块的输出信号的装置。该装置还涉及根据多功能信号的行为产生定时信号给多个触发器。

5. 发明授权

US06442099B1 Low power read scheme for memory array structures 有权
标题翻译：存储器阵列结构的低功耗读取方案
公开(公告)号：US06442099B1
公开(公告)日：2002-08-27
申请号：US09837390
申请日：2001-04-18
申请人： Shree Kant , Gajendra P. Singh
发明人： Shree Kant , Gajendra P. Singh
IPC分类号： G11C800
CPC分类号： G11C5/02 , G11C7/18 , G11C11/412
摘要： A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when accessing data from a segmented bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented bit line structure. Further, a method and apparatus for consuming low power when accessing data from a differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells they are in get closer to an output of the differential bit line structure. Further, a method and apparatus for consuming low power when accessing data from a segmented differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented differential bit line structure.
摘要翻译：提供一种当从存储器阵列访问数据时消耗低功率的方法和装置。此外，当通过使用具有逐渐较小宽度的晶体管作为存储单元或其更靠近分段位的输出的段来提供从寄存器堆中的分段位线结构访问数据时消耗低功率的方法和装置线结构。此外，当通过使用具有逐渐变小的宽度的晶体管作为其更靠近差分位线结构的输出的存储单元来提供从寄存器堆中的差分位线结构访问数据时消耗低功率的方法和装置。此外，当通过使用具有逐渐变小的宽度的晶体管作为存储单元或其更接近分段的输出的分段来提供从寄存器堆中的分段差分位线结构访问数据时消耗低功率的方法和装置差分位线结构。

6. 发明授权

US5999034A Pull-down driver circuit for 3.3V I/O buffer using 1.9V fabrication process 失效
标题翻译：使用1.9V制造工艺的3.3V I / O缓冲器的下拉驱动电路
公开(公告)号：US5999034A
公开(公告)日：1999-12-07
申请号：US14530
申请日：1998-01-28
申请人： Gajendra P. Singh , Vidyasager Ganesan
发明人： Gajendra P. Singh , Vidyasager Ganesan
IPC分类号： H03K17/0814 , H03K17/10 , H03K17/16
CPC分类号： H03K17/162 , H03K17/08142 , H03K17/102
摘要： A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount. The pull-down circuit is a transistor connected to a low voltage source, which limits the pull-down voltage. Additional transistors are provided to turn on and off the pull-down transistor, with a circuit connected to a fail-safe low voltage source being used to protect these transistors.
摘要翻译：用于控制提供给电压转换缓冲器中的开关晶体管的电压的电路，其用低压晶体管驱动高电压输出。电路有两个元素。首先，上拉电路响应于控制逻辑信号的第一状态将开关晶体管的栅极拉到高电压电平。第二，下拉电路响应于控制逻辑信号的第二状态将开关晶体管的栅极拉到中间电压。中间电压被设定为小于高电压不大于近似低电压量。下拉电路是连接到低电压源的晶体管，其限制了下拉电压。提供额外的晶体管来接通和断开下拉晶体管，其中连接到故障安全低电压源的电路用于保护这些晶体管。

7. 发明授权

US5973534A Dynamic bias circuit for driving low voltage I/O transistors 失效
标题翻译：用于驱动低压I / O晶体管的动态偏置电路
公开(公告)号：US5973534A
公开(公告)日：1999-10-26
申请号：US15360
申请日：1998-01-29
申请人： Gajendra P. Singh
发明人： Gajendra P. Singh
IPC分类号： H03K17/10 , H03K5/08
CPC分类号： H03K17/102
摘要： A bias circuit that generates a dynamic bias voltage for driving low-voltage transistors in an output buffer that interfaces with high-voltage signals is disclosed. Various circuits have been devised to ensure that no transistor in the bias and the output buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the output signal voltage may swing well beyond the tolerable voltage levels. This is accomplished with minimal increase in power consumption and without compromising the speed of operation of the output buffer circuit.
摘要翻译：公开了一种产生用于驱动与高电压信号接口的输出缓冲器中的低压晶体管的动态偏置电压的偏置电路。已经设计了各种电路，以确保偏置中的晶体管和输出缓冲器电路的电压都比制造工艺允许的电压高，即使输出信号电压可能远远超出可容忍的电压电平。这是通过功率消耗的最小增加而不影响输出缓冲电路的操作速度来实现的。

8. 发明授权

US6069515A High voltage input buffer circuit using low voltage transistors 失效
标题翻译：高压输入缓冲电路采用低压晶体管
公开(公告)号：US6069515A
公开(公告)日：2000-05-30
申请号：US015847
申请日：1998-01-29
申请人： Gajendra P. Singh
发明人： Gajendra P. Singh
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00315
摘要： An input buffer circuit implemented with low voltage transistors, that is capable of receiving and recognizing input logic signals having higher voltage levels is disclosed. The present invention uses various circuit techniques to ensure that no transistor in the input buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the input signal voltage may swing well beyond the tolerable voltage levels. This is accomplished without compromising the reliability of the input buffer circuit in detecting the logic levels of the input signal.
摘要翻译：公开了一种用低电压晶体管实现的输入缓冲电路，其能够接收和识别具有较高电压电平的输入逻辑信号。本发明使用各种电路技术来确保输入缓冲器电路中的晶体管不经历比制造工艺允许的更高的电压，尽管输入信号电压可以很好地超过容许的电压电平。这是在不损害输入缓冲电路在检测输入信号的逻辑电平方面的可靠性的情况下实现的。

9. 发明授权

US06057710A Diver circuit for 3.3v I/O buffer using 1.9v fabrication process 失效
标题翻译：驱动电路采用3.3V制造工艺的3.3v I / O缓冲器
公开(公告)号：US06057710A
公开(公告)日：2000-05-02
申请号：US14526
申请日：1998-01-28
申请人： Gajendra P. Singh
发明人： Gajendra P. Singh
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount.
摘要翻译：用于控制提供给电压转换缓冲器中的开关晶体管的电压的电路，其用低压晶体管驱动高电压输出。电路有两个元素。首先，上拉电路响应于控制逻辑信号的第一状态将开关晶体管的栅极拉到高电压电平。第二，下拉电路响应于控制逻辑信号的第二状态将开关晶体管的栅极拉到中间电压。中间电压被设定为小于高电压不大于近似低电压量。

10. 发明授权

US06747485B1 Sense amplifier type input receiver with improved clk to Q 失效
标题翻译：感应放大器型输入接收器，具有改进的clk到Q
公开(公告)号：US06747485B1
公开(公告)日：2004-06-08
申请号：US09605264
申请日：2000-06-28
申请人： Samudyatha Suryanarayana , Gajendra P. Singh
发明人： Samudyatha Suryanarayana , Gajendra P. Singh
IPC分类号： H03F345
CPC分类号： G11C7/1087 , G11C7/065 , G11C7/1078
摘要： A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage. A first clock signal and second clock signal may be coupled to the first pass gate to enable passing of the first differential output to the output of the output stage, the first and second clock signals may be coupled to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and the first and second clocks signal coupled to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. A first inverter may be operatively coupled between the first differential output and the first pass gate, a second inverter operatively coupled between the second differential output and the second pass gate, and a third inverter operatively coupled to the output of the output stage.
摘要翻译：感测放大器型输入接收机包括可操作地耦合到输出级的差分接收器电路。输出级包括通过闸门使能的锁存器。差分接收器电路可以输出第一差分输出和第二差分输出。输出级可以包括可操作地耦合在第一差分输出和输出级的输出之间的第一通过门，可操作地耦合在第二差分输出和通过栅极使能的锁存器之间的第二通道门，并且通通门使能的锁存器可以是可操作地耦合到输出级的输出。第一时钟信号和第二时钟信号可以耦合到第一传递门，以使得能够将第一差分输出传递到输出级的输出，第一和第二时钟信号可以耦合到第二通道门，以使所述第二差分输出到所述通过门使能的锁存器，并且所述第一和第二时钟信号耦合到所述通过栅极使能的锁存器的通过栅极以使能所述通过栅极使能的锁存器的操作。第一反相器可以可操作地耦合在第一差分输出和第一通过栅极之间，第二反相器可操作地耦合在第二差分输出和第二通过栅极之间，第三反相器可操作地耦合到输出级的输出端。

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