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1. 发明授权

US06330646B1 Arbitration mechanism for a computer system having a unified memory architecture 有权
标题翻译：具有统一存储架构的计算机系统的仲裁机制
公开(公告)号：US06330646B1
公开(公告)日：2001-12-11
申请号：US09226965
申请日：1999-01-08
申请人： Steve J. Clohset , Trung A. Diep , Wishwesh A. Gandhi , Thomas A. Piazza , Aditya Sreenivas , Tuong P. Trieu
发明人： Steve J. Clohset , Trung A. Diep , Wishwesh A. Gandhi , Thomas A. Piazza , Aditya Sreenivas , Tuong P. Trieu
IPC分类号： G06F1300
CPC分类号： G06F13/18
摘要： According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.
摘要翻译：根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控制器的计算机系统。存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。计算机系统还包括耦合到仲裁单元的第一设备和第二设备。根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

2. 发明授权

US08887174B2 Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers 有权
标题翻译：在多个指令定序器上监视基于指令集的线程执行的机制
公开(公告)号：US08887174B2
公开(公告)日：2014-11-11
申请号：US13191317
申请日：2011-07-26
申请人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
发明人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
IPC分类号： G06F3/00 , G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
摘要翻译：监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少减少与用户级线程相关联的性能抑制事件。

3. 发明申请

US20140115594A1 MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT OPERATING SYSTEM INTERVENTION 审中-公开
标题翻译：在没有操作系统干预的情况下安排在操作系统序列上的线程的机制
公开(公告)号：US20140115594A1
公开(公告)日：2014-04-24
申请号：US14067223
申请日：2013-10-30
申请人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
发明人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
IPC分类号： G06F9/48
CPC分类号： G06F9/4843
摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
摘要翻译：方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。调度程序例程可以在每个启用的顺控程序上运行。调度器可以从队列系统检索碎片描述符。与调度器相关联的定序器然后可以执行由描述符描述的碎片。还描述和要求保护其他实施例。

4. 发明申请

US20120017221A1 Mechanism for Monitoring Instruction Set Based Thread Execution on a Plurality of Instruction Sequencers 审中-公开
标题翻译：监控基于指令集的线程执行在多个指令排序器上的机制
公开(公告)号：US20120017221A1
公开(公告)日：2012-01-19
申请号：US13191317
申请日：2011-07-26
申请人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
发明人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
IPC分类号： G06F9/46
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
摘要翻译：监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少减少与用户级线程相关联的性能抑制事件。

5. 发明授权

US08935489B2 Adaptively time-multiplexing memory references from multiple processor cores 有权
标题翻译：适应时间多路复用多个处理器内核的内存引用
公开(公告)号：US08935489B2
公开(公告)日：2015-01-13
申请号：US13500067
申请日：2010-11-10
申请人： Steven C. Woo , Trung A. Diep , Michael T. Ching
发明人： Steven C. Woo , Trung A. Diep , Michael T. Ching
IPC分类号： G06F12/00 , G06F13/16 , G06F9/52
CPC分类号： G06F13/1652 , G06F9/5016 , G06F9/52
摘要： The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.
摘要翻译：所公开的实施例涉及用于处理从多个处理器核心接收的存储器参考的系统。在操作期间，系统监视存储器引用以确定来自不同处理器核的存储器引用是否因存储器引用被存储器系统处理而彼此干扰。如果来自不同处理器核心的存储器引用彼此干扰，则系统对处理器内核之间的存储器引用进行时间复用，从而在存储器引用之前由存储器系统处理来自给定处理器内核的连续存储器引用块处理其他处理器内核。

6. 发明授权

US08607235B2 Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention 有权
标题翻译：在没有操作系统干预的情况下安排操作系统隔离定序器上的线程的机制
公开(公告)号：US08607235B2
公开(公告)日：2013-12-10
申请号：US11027445
申请日：2004-12-30
申请人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
发明人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
摘要翻译：方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。调度程序例程可以在每个启用的顺控程序上运行。调度器可以从队列系统检索碎片描述符。与调度器相关联的定序器然后可以执行由描述符描述的碎片。还描述和要求保护其他实施例。

7. 发明申请

US20130111132A1 Cache Memory That Supports Tagless Addressing 审中-公开
标题翻译：支持无标签寻址的缓存内存
公开(公告)号：US20130111132A1
公开(公告)日：2013-05-02
申请号：US13807095
申请日：2011-07-25
申请人： Hongzhong Zheng , Trung A. Diep
发明人： Hongzhong Zheng , Trung A. Diep
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/0802 , G06F12/1009 , G06F12/1054
摘要： Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
摘要翻译：公开了与支持无标记寻址的高速缓冲存储器相关的实施例。一些实施例接收执行存储器访问的请求，其中请求包括虚拟地址。作为响应，系统执行地址转换操作，其将虚拟地址转换为物理地址和高速缓存地址。接下来，系统使用物理地址访问物理寻址的高速缓存存储器的一个或多个级别，其中访问物理寻址的高速缓冲存储器的给定级别涉及基于物理地址执行标签检查操作。如果对一个或多个物理寻址的高速缓冲存储器层的访问不能击中用于存储器访问的高速缓存行，则系统使用高速缓存地址来直接索引高速缓存存储器，其中直接索引高速缓冲存储器不涉及执行标签检查操作，并消除标签存储开销。

8. 发明授权

US10133676B2 Cache memory that supports tagless addressing 有权
公开(公告)号：US10133676B2
公开(公告)日：2018-11-20
申请号：US13807095
申请日：2011-07-25
申请人： Hongzhong Zheng , Trung A. Diep
发明人： Hongzhong Zheng , Trung A. Diep
IPC分类号： G06F12/00 , G06F12/1045 , G06F12/0802 , G06F12/1009
摘要： Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

9. 发明申请

US20120278583A1 ADAPTIVELY TIME-MULTIPLEXING MEMORY REFERENCES FROM MULTIPLE PROCESSOR CORES 有权
标题翻译：多种处理器的适应时间多通道存储器参考
公开(公告)号：US20120278583A1
公开(公告)日：2012-11-01
申请号：US13500067
申请日：2010-11-10
申请人： Steven C. Woo , Trung A. Diep , Michael T. Ching
发明人： Steven C. Woo , Trung A. Diep , Michael T. Ching
IPC分类号： G06F12/00
CPC分类号： G06F13/1652 , G06F9/5016 , G06F9/52
摘要： The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.
摘要翻译：所公开的实施例涉及用于处理从多个处理器核心接收的存储器参考的系统。在操作期间，系统监视存储器引用以确定来自不同处理器核的存储器引用是否因存储器引用被存储器系统处理而彼此干扰。如果来自不同处理器核心的存储器引用彼此干扰，则系统对处理器内核之间的存储器引用进行时间复用，从而在存储器引用之前由存储器系统处理来自给定处理器内核的连续存储器引用块处理其他处理器内核。

10. 发明授权

US08010969B2 Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers 有权
标题翻译：在多个指令定序器上监视基于指令集的线程执行的机制
公开(公告)号：US08010969B2
公开(公告)日：2011-08-30
申请号：US11151809
申请日：2005-06-13
申请人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
发明人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
IPC分类号： G06F3/00 , G06F9/46 , G06F7/38
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
摘要翻译：监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少减少与用户级线程相关联的性能抑制事件。

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