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1. 发明申请

US20150199198A1 SUPERVISOR MODE EXECUTION PROTECTION 有权
标题翻译：监督模式执行保护
公开(公告)号：US20150199198A1
公开(公告)日：2015-07-16
申请号：US13997857
申请日：2011-12-29
申请人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
发明人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30043 , G06F12/0292 , G06F12/1009 , G06F12/1491
摘要： Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.
摘要翻译：公开了用于监督模式执行保护的装置和方法。在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。存储器中的区域是用户存储器。执行硬件是执行指令。当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

2. 发明申请

US20140115594A1 MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT OPERATING SYSTEM INTERVENTION 审中-公开
标题翻译：在没有操作系统干预的情况下安排在操作系统序列上的线程的机制
公开(公告)号：US20140115594A1
公开(公告)日：2014-04-24
申请号：US14067223
申请日：2013-10-30
申请人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
发明人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
IPC分类号： G06F9/48
CPC分类号： G06F9/4843
摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
摘要翻译：方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。调度程序例程可以在每个启用的顺控程序上运行。调度器可以从队列系统检索碎片描述符。与调度器相关联的定序器然后可以执行由描述符描述的碎片。还描述和要求保护其他实施例。

3. 发明申请

US20110161981A1 USING PER TASK TIME SLICE INFORMATION TO IMPROVE DYNAMIC PERFORMANCE STATE SELECTION 有权
标题翻译：使用每个任务时间片段信息来提高动态性能状态选择
公开(公告)号：US20110161981A1
公开(公告)日：2011-06-30
申请号：US12968243
申请日：2010-12-14
申请人： Adriaan Van De Ven , A. Leonard Brown , Asit K. Mallick
发明人： Adriaan Van De Ven , A. Leonard Brown , Asit K. Mallick
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F1/3296 , G06F9/5094 , Y02D10/22
摘要： Methods and apparatus for using per task time slice information to improve dynamic performance state selection are described. In one embodiment, a new performance state is selected for a process based on one or more previous execution time slice values of the process. Other embodiments are also described.
摘要翻译：描述了使用每个任务时间片信息来改善动态性能状态选择的方法和装置。在一个实施例中，基于进程的一个或多个先前的执行时间片值为进程选择新的执行状态。还描述了其它实施例。

4. 发明授权

US06745346B2 Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recovery 有权
标题翻译：用于通过操作系统（OS）有效地识别计算机系统中的错误过程的用于错误容纳和错误恢复的方法
公开(公告)号：US06745346B2
公开(公告)日：2004-06-01
申请号：US09732306
申请日：2000-12-08
申请人： Nhon T. Quach , Amy L. O'Donnell , Asit K. Mallick , Koichi Yamada
发明人： Nhon T. Quach , Amy L. O'Donnell , Asit K. Mallick , Koichi Yamada
IPC分类号： G06F1100
CPC分类号： G06F11/08
摘要： The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP). The method further includes determining a first virtual address from an operating system mapping table, determining a second virtual address from a translation look-aside buffer, and identifying the errant process, if the physical address and the second virtual address match the physical address and the first virtual address.
摘要翻译：本发明涉及一种使用操作系统（OS）错误恢复方法来有效地识别计算机系统中的错误过程的方法和系统，该方法和系统识别错误过程引起的错误是否可以被恢复，并且如果可以从错误。本发明的方法和系统在标准错误校正码（ECC）和奇偶校验位方法和系统在从错误中恢复失败之后起作用。根据本发明的一个实施例，该方法和系统包括：指令执行，存储导致错误的错误处理的物理地址，以及将执行指令指针（IP）存储在中断指令指针（IIP）中。该方法还包括：如果物理地址和第二虚拟地址与物理地址匹配，则从操作系统映射表确定第一虚拟地址，从转换后备缓冲区确定第二虚拟地址，并识别错误过程第一个虚拟地址。

5. 发明申请

US20140365742A1 SYSTEMS AND METHODS FOR PREVENTING UNAUTHORIZED STACK PIVOTING 有权
标题翻译：用于防止未经授权的堆叠物品的系统和方法
公开(公告)号：US20140365742A1
公开(公告)日：2014-12-11
申请号：US13910333
申请日：2013-06-05
申请人： BAIJU V. PATEL , XIAONING LI , H P. ANVIN , ASIT K. MALLICK , GILBERT NEIGER , JAMES B. CROSSLAND , TOBY OPFERMAN , ATUL A. KHARE , JASON W. BRANDT , JAMES S. COKE , BRIAN L. VAJDA
发明人： BAIJU V. PATEL , XIAONING LI , H P. ANVIN , ASIT K. MALLICK , GILBERT NEIGER , JAMES B. CROSSLAND , TOBY OPFERMAN , ATUL A. KHARE , JASON W. BRANDT , JAMES S. COKE , BRIAN L. VAJDA
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F8/434 , G06F9/30105 , G06F9/30134 , G06F21/52
摘要： An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.
摘要翻译：示例处理系统可以包括：下堆叠绑定寄存器，被配置为存储第一存储器地址，第一存储器地址识别经由堆栈段可寻址的存储器的下限; 上堆叠绑定寄存器，其被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 并且通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来配置用于检测未授权堆栈枢转的堆栈边界检查逻辑。

6. 发明授权

US08635415B2 Managing and implementing metadata in central processing unit using register extensions 有权
标题翻译：使用寄存器扩展管理和实施中央处理单元中的元数据
公开(公告)号：US08635415B2
公开(公告)日：2014-01-21
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jacob (Koby) Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jacob (Koby) Gottlieb
IPC分类号： G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

7. 发明授权

US08607235B2 Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention 有权
标题翻译：在没有操作系统干预的情况下安排操作系统隔离定序器上的线程的机制
公开(公告)号：US08607235B2
公开(公告)日：2013-12-10
申请号：US11027445
申请日：2004-12-30
申请人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
发明人： Richard A. Hankins , Hong Wang , Gautham N. Chinya , Trung A. Diep , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Asit K. Mallick , Baiju V. Patel , James Paul Held , Milind B. Girkar , Prashant Sethi , Xinmin Tian
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
摘要翻译：方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。调度程序例程可以在每个启用的顺控程序上运行。调度器可以从队列系统检索碎片描述符。与调度器相关联的定序器然后可以执行由描述符描述的碎片。还描述和要求保护其他实施例。

8. 发明申请

US20130031333A1 METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY 有权
标题翻译：支持共享虚拟内存的异构计算系统中TLB SHOOT-DOWN的方法和设备
公开(公告)号：US20130031333A1
公开(公告)日：2013-01-31
申请号：US13191327
申请日：2011-07-26
申请人： Rajesh M. Sankaran , Altug Koker , Philip R. Lantz , Asit K. Mallick , James B. Crossland , Aditya Navale , Gilbert Neiger , Andrew V. Anderson
发明人： Rajesh M. Sankaran , Altug Koker , Philip R. Lantz , Asit K. Mallick , James B. Crossland , Aditya Navale , Gilbert Neiger , Andrew V. Anderson
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1081 , G06F2212/1016 , G06F2212/1048 , G06F2212/303 , G06F2212/682 , G06F2212/683
摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.
摘要翻译：公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目。 PASID状态条目可以包括活动参考状态和惰性无效状态。响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

9. 发明授权

US09785463B2 Using per task time slice information to improve dynamic performance state selection 有权
公开(公告)号：US09785463B2
公开(公告)日：2017-10-10
申请号：US12968243
申请日：2010-12-14
申请人： Adriaan Van De Ven , A. Leonard Brown , Asit K. Mallick
发明人： Adriaan Van De Ven , A. Leonard Brown , Asit K. Mallick
IPC分类号： G06F9/48 , G06F9/50 , G06F1/32
CPC分类号： G06F9/4843 , G06F1/3296 , G06F9/5094 , Y02D10/22
摘要： Methods and apparatus for using per task time slice information to improve dynamic performance state selection are described. In one embodiment, a new performance state is selected for a process based on one or more previous execution time slice values of the process. Other embodiments are also described.

10. 发明申请

US20170249260A1 SYSTEM FOR ADDRESS MAPPING AND TRANSLATION PROTECTION 审中-公开
公开(公告)号：US20170249260A1
公开(公告)日：2017-08-31
申请号：US15088739
申请日：2016-04-01
申请人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
发明人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
IPC分类号： G06F12/14 , G06F12/10 , G06F21/62 , G06F3/06
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

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