专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06309936B1 Integrated formation of LDD and non-LDD semiconductor devices 有权
标题翻译： LDD和非LDD半导体器件的集成形成
公开(公告)号：US06309936B1
公开(公告)日：2001-10-30
申请号：US09163965
申请日：1998-09-30
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.
摘要翻译：形成半导体器件的方法包括在衬底上形成第一栅电极，然后在第一栅电极的至少一个侧壁上形成间隔物。在形成间隔物之后，在衬底上形成第二栅电极。将第一掺杂剂注入到衬底中以形成与间隔物相邻的第一重掺杂有源区，并与第一栅极间隔开，并与第二栅电极相邻的第二重掺杂有源区。然后去除间隔物，并将第二掺杂剂注入到衬底中以形成与第一栅电极相邻的轻掺杂有源区。在一些情况下，用于第一和第二栅电极的栅极电介质是使用不同的材料和/或具有不同的厚度来形成的。

2. 发明授权

US6140163A Method and apparatus for upper level substrate isolation integrated with bulk silicon 失效
标题翻译：用于与体硅一体化的上层衬底隔离的方法和装置
公开(公告)号：US6140163A
公开(公告)日：2000-10-31
申请号：US893744
申请日：1997-07-11
申请人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
IPC分类号： H01L21/822 , H01L21/00 , H01L21/84 , H01L27/01 , H01L27/12
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.
摘要翻译：高性能半导体器件结构及其制造方法包括体半导体衬底和上层硅衬底。上层硅衬底包括低K电介质层和硅衬底层。低K电介质层形成在体半导体衬底上，低K电介质层的介电K值在2.0-3.8范围内。然后将硅衬底层和低K电介质层在第一区域中被图案化到上层衬底中，并且在第二区域中暴露体半导体衬底。栅极氧化物层形成在第一区域中的上层衬底之上并且在第二区域中的暴露的体半导体衬底之上。最后，晶体管器件形成在上层衬底和体半导体衬底中。

3. 发明授权

US6100204A Method of making ultra thin gate oxide using aluminum oxide 失效
标题翻译：使用氧化铝制造超薄栅极氧化物的方法
公开(公告)号：US6100204A
公开(公告)日：2000-08-08
申请号：US123657
申请日：1998-07-28
申请人： Mark I. Gardner , Mark C. Gilmer , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Mark C. Gilmer , Thomas E. Spikes, Jr.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/469
CPC分类号： H01L21/28185 , H01L29/517 , H01L29/6659 , H01L21/28194
摘要： A transistor and a method of making the same are provided. The method includes the step of forming a gate dielectric layer on the substrate where the gate dielectric layer is composed of an aluminum oxide containing material. A gate electrode is formed on the gate dielectric layer and first and second source/drain regions are formed in the substrate laterally separated to define a channel region beneath the gate electrode. The aluminum oxide containing material may be, for example, Al.sub.2 O.sub.3. Aluminum oxide provides for a gate dielectric with a thin equivalent thickness of oxide in a potentially single crystal form.
摘要翻译：提供晶体管及其制造方法。该方法包括在栅极电介质层由含氧化铝材料构成的基板上形成栅极电介质层的步骤。栅极电极形成在栅极介电层上，并且第一和第二源极/漏极区域形成在衬底中横向分离以限定栅电极下方的沟道区域。含氧化铝的材料可以是例如Al 2 O 3。氧化铝以可能的单晶形式提供具有薄的当量厚度的氧化物的栅极电介质。

4. 发明授权

US6064102A Semiconductor device having gate electrodes with different gate insulators and fabrication thereof 失效
标题翻译：具有栅电极和不同栅极绝缘体的半导体器件及其制造
公开(公告)号：US6064102A
公开(公告)日：2000-05-16
申请号：US992318
申请日：1997-12-17
申请人： Mark I. Gardner , H. Jim Fulford , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford , Thomas E. Spikes, Jr.
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L21/823462
摘要： A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.
摘要翻译：提供了具有不同栅极绝缘体的栅电极和制造这种器件的工艺的半导体器件。根据本发明的一个实施例，提供一种半导体器件，其中在衬底的第一区域上形成第一栅极绝缘体。与第一栅极绝缘体不同的第二栅极绝缘体形成在衬底的第二区域上。最后，在第一和第二栅极绝缘体的每一个上形成一个或多个栅电极。第一栅极绝缘体可以例如具有不同于第二栅极绝缘体的介电常数和/或厚度。例如，第一栅极绝缘体可以具有大于20的介电常数，并且第二栅极绝缘体可以具有小于10的介电常数。

5. 发明授权

US5970375A Semiconductor fabrication employing a local interconnect 失效
标题翻译：采用局部互连的半导体制造
公开(公告)号：US5970375A
公开(公告)日：1999-10-19
申请号：US851086
申请日：1997-05-03
申请人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/76895
摘要： An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher packing density by removing the local interconnect to a sub-level dielectrically spaced from possibly other local interconnects and from the distal interconnect normally associated with device interconnection. A semiconductor topography is provided which includes a first transistor laterally spaced from a second transistor, the transistors being arranged upon and within the substrate. An interlevel dielectric is deposited across the semiconductor topography. A portion of the interlevel dielectric is removed to form a trench. The trench is then filled with a conductive material to form a local interconnect extending horizontally above a portion of the first transistor and a portion of the second transistor. Portions of the interlevel dielectric and the local interconnect are removed in sequence while retaining the patterned masking layer. Removal of the local interconnect forms vias extending to the gate conductor of one transistor and to a junction of the other transistor, or from the gate conductor of one transistor to a junction of the same transistor. A conductive material may be deposited in these vias to form plugs therein. Further, a capping dielectric layer may be deposited upon the interlevel dielectric and contact regions may be formed which abut the plugs. Therefore, distal interconnect conductive layers may then be formed dielectrically above the local interconnect which are then electrically coupled to the local interconnect through the contact regions.
摘要翻译：提供一种集成电路制造工艺，其中在一个晶体管的栅极导体和另一个晶体管的结之间形成子级局部互连。子级局部互连的形成允许通过将本地互连移除到与可能的其它本地互连以及通常与设备互连相关联的远端互连的介电间隔的子级别来实现更高的堆叠密度。提供半导体形貌，其包括与第二晶体管横向隔开的第一晶体管，晶体管布置在衬底上和衬底内。跨越半导体形貌沉积层间电介质。去除层间电介质的一部分以形成沟槽。然后用导电材料填充沟槽，以形成在第一晶体管的一部分和第二晶体管的一部分上方水平延伸的局部互连。层叠电介质和局部互连的部分在保持图案化掩模层的同时被顺序地去除。去除局部互连形成延伸到一个晶体管的栅极导体和另一个晶体管的结或从一个晶体管的栅极导体到同一晶体管的结的结的通孔。导电材料可以沉积在这些通孔中以在其中形成插塞。此外，可以在层间电介质上沉积覆盖电介质层，并且可以形成接触插塞的接触区域。因此，远端互连导电层然后可以介电地形成在局部互连上方，然后电连接到局部互连通过接触区域。

6. 发明授权

US5942787A Small gate electrode MOSFET 失效
标题翻译：小栅极电极MOSFET
公开(公告)号：US5942787A
公开(公告)日：1999-08-24
申请号：US751582
申请日：1996-11-18
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21/033 , H01L21/28 , H01L21/8234 , H01L21/8232
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L21/823437 , Y10S438/926 , Y10S438/947
摘要： A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material. Sidewall spacers are formed in the conformal layer proximate side edges of the patterned layer, the sidewall spacers having a desired line width dimension of the small features to be fabricated. The patterned layer is thereafter selectively removed. The first layer is then directionally etched with a selective etch, using the sidewall spacers to prevent the etching of the first layer in accordance with the desired pattern.
摘要翻译：公开了一种根据期望的图案在装置中光刻地制造小线宽特征的方法，小线宽特征小于仅能够进行光刻工艺的小线宽特征。第一层材料设置在基板上，第一层包括将要制造小线宽特征的第一层。然后根据与期望图案一起限定的第二图案在第一层上提供光刻图案层。图案化层包括选择为与第一层的材料相容的第二材料。然后将保形层沉积在图案化层上，保形层包括选择为与第一材料和第二材料相结合的第三材料。在图案化层的近侧边缘的共形层中形成侧壁间隔物，侧壁间隔物具有要制造的小特征的期望的线宽度尺寸。此后，图案化层被选择性地去除。然后用选择性蚀刻对第一层进行定向蚀刻，使用侧壁间隔物来防止根据所需图案蚀刻第一层。

7. 发明授权

US06326251B1 Method of making salicidation of source and drain regions with metal gate MOSFET 有权
标题翻译：用金属栅极MOSFET对源极和漏极区域进行腐蚀的方法
公开(公告)号：US06326251B1
公开(公告)日：2001-12-04
申请号：US09290790
申请日：1999-01-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28079 , H01L21/28088 , H01L21/823814 , H01L21/823835 , H01L29/495 , H01L29/66545
摘要： A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.
摘要翻译：形成晶体管的方法包括在刚刚形成衬底上的隔离和有源区域之后的初始处理阶段中形成源极/漏极注入。在介电层顶部的衬底的表面上形成均匀的氮化物层。然后沉积硅化物金属并与下面的硅反应以在源区和漏区上形成自对准硅化物。然后在硅化物的顶部上形成第二电介质层，并且形成为相对于氮化物层是选择性的。此后，去除氮化物层，然后形成最终的栅极电介质。最后，在栅极电介质的顶部形成金属栅极导体。仅在执行所有退火步骤之后才形成金属栅极导体，以防止金属通过栅极电介质尖峰，从而破坏器件。

8. 发明授权

US06239476B1 Integrated circuit isolation structure employing a protective layer and method for making same 有权
标题翻译：采用保护层的集成电路隔离结构及其制造方法
公开(公告)号：US06239476B1
公开(公告)日：2001-05-29
申请号：US09176132
申请日：1998-10-21
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.
摘要翻译：提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。限定沟槽表面边界，其中沟槽侧壁与半导体衬底的上表面相交。沟槽可以填充沟槽填充材料。然后在沟槽上方形成保护层。保护层覆盖沟槽并横向延伸超过沟槽表面边界至少第一距离半导体衬底上方。

9. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

10. 发明授权

US5933747A Method and structure for an advanced isolation spacer shell 失效
标题翻译：高级隔离隔离壳的方法和结构
公开(公告)号：US5933747A
公开(公告)日：1999-08-03
申请号：US993390
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr.
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method and structure are provided for a spacer shell structure which is formed of dielectric materials seletive to one another. The dielectric materials can be configured into a chosen geometric arrangement. The isolation properties of the spacer shell can be scaled to meet a given set of isolation requirements as determined by the size and density of the IGFET devices being isolated. The method to fabricate the novel spacer shell maintains costly fabrication steps at a minimum. The isolation ability of the novel spacer shell preserves the operation integrity of neighboring IGFET devices. Electrical shorts between adjacent devices are prevented. Capacitive coupling between neighboring IGFET structures is likewise minimized.
摘要翻译：提供了一种隔离壳结构的方法和结构，该隔离壳结构由彼此相互连接的电介质材料形成。介电材料可以被配置成所选择的几何布置。间隔壳的隔离性能可以缩放以满足由隔离的IGFET器件的尺寸和密度所确定的给定的隔离要求。制造新型间隔壳的方法至少保持了昂贵的制造步骤。新型间隔壳的隔离能力保持了相邻IGFET器件的操作完整性。防止相邻设备之间的电气短路。相邻IGFET结构之间的电容耦合同样被最小化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式