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1. 发明授权

US06528829B1 Integrated circuit structure having a charge injection barrier 失效
标题翻译：具有电荷注入阻挡层的集成电路结构
公开(公告)号：US06528829B1
公开(公告)日：2003-03-04
申请号：US09276041
申请日：1999-03-25
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Michael Wojtowicz , Dwight C. Streit , Thomas R. Block , Frank M. Yamada
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Michael Wojtowicz , Dwight C. Streit , Thomas R. Block , Frank M. Yamada
IPC分类号： H01L2970
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02546 , H01L29/267 , H01L29/7371
摘要： The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.
摘要翻译：本发明涉及一种集成电路结构，其包括具有设置在衬底晶片的表面上并且其中包含导电元件的有源器件层的衬底晶片。集成电路结构还包括设置在衬底晶片和有源器件层之间的势垒，其中势垒阻挡载流子注入衬底晶片并降低低频振荡效应。

2. 发明授权

US06680494B2 Ultra high speed heterojunction bipolar transistor having a cantilevered base 有权
标题翻译：具有悬臂底座的超高速异质结双极晶体管
公开(公告)号：US06680494B2
公开(公告)日：2004-01-20
申请号：US09776513
申请日：2001-02-02
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Eric N. Kaneshiro , Dwight C. Streit
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Eric N. Kaneshiro , Dwight C. Streit
IPC分类号： H01L29732
CPC分类号： H01L29/66318 , H01L29/045 , H01L29/1004 , H01L29/7371
摘要： Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.
摘要翻译：通过使用现有的材料和工艺，通过在基底（7）下沿基底台面（7）的两个平行边缘切割集电体（5）来实现异质结双极晶体管的基极到集电极电容的减小，以及改进的高频性能。并且沿着底座的剩余的两个平行侧提供倾斜的收集器边缘（5-Fig。6）。前述是通过选择性蚀刻实现的，并且台面区域的四个侧面被定向为非矩形平行四边形（7,9-图4），其中一对边与所述[0,01 ]和晶体结构的[0 0（超芯（1）]平面，另一对侧与晶体结构的[0,1]和[0 {超晶核（1（超晶核（1））平面之一平行。

3. 发明授权

US06376867B1 Heterojunction bipolar transistor with reduced thermal resistance 有权
标题翻译：具有降低的热阻的异质结双极晶体管
公开(公告)号：US06376867B1
公开(公告)日：2002-04-23
申请号：US09631597
申请日：2000-08-03
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Patrick T. Chin , Dwight C. Streit
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Patrick T. Chin , Dwight C. Streit
IPC分类号： H01L310328
CPC分类号： H01L29/0821 , H01L29/7371
摘要： The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and especially InP-based HBTs, heat generated during operation is concentrated near the collector-base junction. In order to more efficiently dissipate heat downward through the device to the substrate, both the collector and the sub-collector are formed of InP, which has a substantially lower thermal resistance than other typically used semiconductor materials.
摘要翻译：以高功率工作的异质结双极晶体管（HBT）的性能受到器件消耗的功率的限制。这又受到设备的散热热阻的限制。在典型的HBT中，特别是基于InP的HBT中，在操作期间产生的热量集中在集电极 - 基极结附近。为了更有效地将热量通过器件向下散发到衬底，集电极和副集电极都由InP形成，其具有比其它通常使用的半导体材料显着更低的热阻。

4. 发明授权

US5323138A Reliable thin film resistors for integrated circuit applications 失效
标题翻译：用于集成电路应用的可靠的薄膜电阻
公开(公告)号：US5323138A
公开(公告)日：1994-06-21
申请号：US940556
申请日：1992-09-04
申请人： Aaron K. Oki , Donald K. Umemoto , Frank M. Yamada , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Frank M. Yamada , Dwight C. Streit
IPC分类号： H01C7/00 , H01C1/012
CPC分类号： H01C7/006
摘要： A thin film resistor with an insulating layer disposed between a substrate material and a resistor material is disclosed. Also, disclosed is a technique for fabricating this thin film resistor. In accordance with the preferred embodiment, the thin film resistor employs an insulating layer of silicon nitride with a thickness of 2000 .ANG.. The insulating layer prevents the resistor layer from diffusing into the substrate material which, in turn, significantly reduces variations in the resistor value during accelerated life testing. Compared to thin film resistors with a resistor layer evaporated directly upon a substrate material, reliability is increased from a few hundred hours up to thousands of hours. Also, the maximum current handling capability is increased by greater than one order of magnitude, which results in a thin film resistor which requires less surface area of a wafer.
摘要翻译：公开了一种具有设置在基板材料和电阻材料之间的绝缘层的薄膜电阻器。此外，公开了一种制造该薄膜电阻器的技术。根据优选实施例，薄膜电阻器使用厚度为2000安培的氮化硅绝缘层。绝缘层防止电阻层扩散到衬底材料中，这又显着地减少了加速寿命测试期间电阻值的变化。与直接在衬底材料上蒸发的电阻层的薄膜电阻器相比，可靠性从几百小时提高到数千小时。此外，最大电流处理能力增加大于一个数量级，这导致需要较少的晶片表面积的薄膜电阻器。

5. 发明授权

US6037646A High-frequency GaAs substrate based schottky barrier diodes 失效
标题翻译：基于高频GaAs衬底的肖特基势垒二极管
公开(公告)号：US6037646A
公开(公告)日：2000-03-14
申请号：US865890
申请日：1997-05-30
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872 , H01L27/095
CPC分类号： H01L29/66212 , H01L29/872
摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.
摘要翻译：一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。合适的电介质材料沉积在集电极层的顶部。在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

6. 发明授权

US5631477A Quaternary collector InAlAs-InGaAlAs heterojunction bipolar transistor 失效
标题翻译：四元收集器InAlAs-InGaAlAs异质结双极晶体管
公开(公告)号：US5631477A
公开(公告)日：1997-05-20
申请号：US490440
申请日：1995-06-02
申请人： Dwight C. Streit , Aaron K. Oki , Liem T. Tran
发明人： Dwight C. Streit , Aaron K. Oki , Liem T. Tran
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L29/7371
摘要： An InAlAs/InGaAlAs heterojunction bipolar transistor that includes a constant quaternary InGaAlAs collector layer. Graded InGaAlAs collector layers are provided on each side of the quaternary collector layer to minimize transitions through the constant collector layer. The InAlAs/InGaAlAs HBT may also include one or more of a graded InGaAlAs emitter-base transition region, a graded-doping InGaAs base layer, and a graded-composition InGaAlAs base layer.
摘要翻译： InAlAs / InGaAlAs异质结双极晶体管，其包括恒定的四元InGaAlAs集电极层。渐变的InGaAlAs集电极层设置在四元集电极层的每一侧，以使通过恒定集电极层的过渡最小化。 InAlAs / InGaAlAs HBT还可以包括渐变的InGaAlAs发射极 - 基极化过渡区，渐变掺杂的InGaAs基层和渐变组成的InGaAlAs基层中的一个或多个。

7. 发明授权

US5162243A Method of producing high reliability heterojunction bipolar transistors 失效
标题翻译：制造高可靠性异质结双极晶体管的方法
公开(公告)号：US5162243A
公开(公告)日：1992-11-10
申请号：US752401
申请日：1991-08-30
申请人： Dwight C. Streit , Aaron K. Oki
发明人： Dwight C. Streit , Aaron K. Oki
IPC分类号： H01L29/205 , H01L21/203 , H01L21/331 , H01L29/207 , H01L29/73 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/207 , H01L29/7371 , Y10S438/936
摘要： A technique for producing high reliability GaAsAlGaAs heterojunction bipolar transistors by Molecular Beam Epitaxy with beryllium base doping. Beryllium incorporation and diffusion, during base-layer deposition, is controlled through a combination of reduced substrate temperature and increase As/Ga flux ratio during MBE growth resulting in extremely stable heterojunction bipolar transistor profiles. In addition, graded InGaAs surface layers with non-alloyed refractory metal contacts are shown to significantly improve ohmic reliability to alloyed AuGe contacts. High gain (DC beta) is achieved by the use of an increased substrate temperature during emitter deposition. The HBTs in accordance with the present invention are useful in a number of important microwave applications such as log amps, a/d converters, and sample and hold circuits where high reliability is desired.

8. 发明授权

US06465289B1 Method of fabricating monolithic multifunction integrated circuit devices 失效
标题翻译：单片多功能集成电路器件的制造方法
公开(公告)号：US06465289B1
公开(公告)日：2002-10-15
申请号：US08675248
申请日：1996-07-01
申请人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
发明人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
IPC分类号： H01L21338
CPC分类号： H01L27/0605 , H01L21/8252
摘要： A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.
摘要翻译：一种用于在包括PIN二极管器件，HBT器件，HEMT器件和MESFET器件的组合的公共衬底上制造单片集成电路器件的选择性分子束外延的方法。该方法包括将一个器件的轮廓层沉积在合适的衬底上，然后在轮廓层上沉积第一介电层。然后蚀刻轮廓层和电介质层以限定第一装置轮廓。用于限定第二装置的第二轮廓层然后沉积在暴露的基底上。然后选择性地蚀刻第二轮廓以限定第二装置轮廓。只要第一个开发的设备足够坚固以处理与后续设备相关的温度循环，该过程可以扩展到单个集成在公共基板上的多于两种不同的设备类型。

9. 发明授权

US5262335A Method to produce complementary heterojunction bipolar transistors 失效
标题翻译：产生互补异质结双极晶体管的方法
公开(公告)号：US5262335A
公开(公告)日：1993-11-16
申请号：US772809
申请日：1991-10-08
申请人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
发明人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
IPC分类号： H01L29/205 , H01L21/331 , H01L21/8228 , H01L21/8252 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/737 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/0826 , Y10S148/072
摘要： Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.

10. 发明授权

US5930636A Method of fabricating high-frequency GaAs substrate-based Schottky barrier diodes 失效
标题翻译：制造高频GaAs衬底的肖特基势垒二极管的方法
公开(公告)号：US5930636A
公开(公告)日：1999-07-27
申请号：US645361
申请日：1996-05-13
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872 , H01L21/331 , H01L21/00 , H01L21/338 , H01L31/0328
CPC分类号： H01L29/66212 , H01L29/872
摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.
摘要翻译：一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。合适的电介质材料沉积在集电极层的顶部。在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

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