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1. 发明授权

US08338251B2 Method of manufacture transistor with reduced charge carrier mobility 有权
标题翻译：制造具有降低的载流子迁移率的晶体管的方法
公开(公告)号：US08338251B2
公开(公告)日：2012-12-25
申请号：US13472514
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

2. 发明授权

US08487380B2 Transistor with reduced charge carrier mobility 有权
标题翻译：具有降低的载流子迁移率的晶体管
公开(公告)号：US08487380B2
公开(公告)日：2013-07-16
申请号：US13472515
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
IPC分类号： H01L27/12
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一个或多个实施例涉及一种装置，包括：第一晶体管，包括鳍片; 以及包括鳍的第二晶体管，所述第一晶体管的鳍具有比所述第二晶体管的鳍更低的载流子迁移率。

3. 发明授权

US08245565B2 Slurry transport and storage system 有权
标题翻译：泥浆运输和储存系统
公开(公告)号：US08245565B2
公开(公告)日：2012-08-21
申请号：US12131936
申请日：2008-06-03
申请人： Stefan Geyer
发明人： Stefan Geyer
IPC分类号： G01N11/04
CPC分类号： G01N11/06
摘要： An embodiment of the present invention is a transport and storage system for a slurry comprising: a main container; and a test container, the main container and the test container being exposed to the same environmental conditions, the main container and the test container containing a slurry from the same batch, wherein the test container is designed to determine the viscosity of the slurry.
摘要翻译：本发明的一个实施例是用于浆料的运输和储存系统，包括：主容器; 以及测试容器，主容器和测试容器暴露在相同的环境条件下，主容器和测试容器含有来自相同批料的浆料，其中测试容器被设计成确定浆料的粘度。

4. 发明授权

US07973358B2 Coupler structure 有权
标题翻译：耦合器结构
公开(公告)号：US07973358B2
公开(公告)日：2011-07-05
申请号：US12187406
申请日：2008-08-07
申请人： Andre Hanke , Oliver Nagy
发明人： Andre Hanke , Oliver Nagy
IPC分类号： H01L21/00
CPC分类号： H01P5/18
摘要： One or more embodiments relate to a semiconductor device, comprising: a substrate; and a radio frequency coupler including a first coupling element and a second coupling element spacedly disposed from the first coupling element, the first coupling element including at least one through-substrate via disposed in the substrate, the second coupling element including at least one through-substrate via disposed in the substrate.
摘要翻译：一个或多个实施例涉及半导体器件，包括：衬底; 以及包括第一耦合元件和与所述第一耦合元件间隔设置的第二耦合元件的射频耦合器，所述第一耦合元件包括设置在所述衬底中的至少一个贯通衬底通孔，所述第二耦合元件包括至少一个通孔，衬底通孔设置在衬底中。

5. 发明授权

US08518798B2 Semiconductor structure and method for making same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08518798B2
公开(公告)日：2013-08-27
申请号：US12888454
申请日：2010-09-23
申请人： Eric Graetz
发明人： Eric Graetz
IPC分类号： H01L21/30
CPC分类号： H01L29/06 , H01L21/76256
摘要： One or more embodiments relate to a method for forming a semiconductor structure, including: forming a semiconductor layer; and forming a dielectric layer over a back side of said semiconductor layer. In one or more embodiments, the dielectric layer may be a silicone rubber layer.
摘要翻译：一个或多个实施例涉及一种用于形成半导体结构的方法，包括：形成半导体层; 以及在所述半导体层的背面上形成介电层。在一个或多个实施例中，电介质层可以是硅橡胶层。

6. 发明授权

US08331166B2 Method and system for reading from memory cells in a memory device 有权
标题翻译：用于从存储器件中的存储单元读取的方法和系统
公开(公告)号：US08331166B2
公开(公告)日：2012-12-11
申请号：US13036030
申请日：2011-02-28
申请人： Cyrille Dray , Alexandre Ney
发明人： Cyrille Dray , Alexandre Ney
IPC分类号： G11C5/14
CPC分类号： G11C7/02 , G11C7/08 , G11C7/14 , G11C2207/002
摘要： A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.
摘要翻译：提供了一种用于从存储器件中的存储单元读取的方法和系统。在一个实施例中，存储器设备包括第一多个数据线和第二多个数据线，耦合到第一多个数据线和至少一个低参考线的至少一个第一多路复用器，耦合到所述第二多个数据线和至少一个高参考线，耦合到所述至少一个第一多路复用器和所述至少一个第二多路复用器的至少一个第三多路复用器，以及耦合到所述至少一个第三多路复用器的参考存储器单元，至少一个读出放大器。

7. 发明授权

US08315024B2 Electrostatic discharge protection circuit, integrated circuit and method of protecting circuitry from an electrostatic discharge voltage 有权
标题翻译：静电放电保护电路，集成电路和保护电路免受静电放电电压的影响
公开(公告)号：US08315024B2
公开(公告)日：2012-11-20
申请号：US12560475
申请日：2009-09-16
申请人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krysztof Domanski
发明人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krysztof Domanski
IPC分类号： H02H3/22
CPC分类号： H01L27/0281 , H01L27/0285
摘要： Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.
摘要翻译：本文给出了包括静电放电（ESD）保护电路的实现。 ESD保护电路包括第一晶体管和第二晶体管。第一晶体管具有耦合到第一电源线的第一端子和耦合到第二电源线的本体。第二晶体管具有耦合到第二电源线的第一端子，耦合到第一电源线的体和耦合到第一晶体管的第二端子以限定受保护节点的第二端子。 ESD保护电路还包括具有耦合到受保护节点的第一端子的限流元件。

8. 发明授权

US08199560B2 Memory device comprising select gate including carbon allotrope 有权
标题翻译：存储器件包括选择栅极，包括碳同素异形体
公开(公告)号：US08199560B2
公开(公告)日：2012-06-12
申请号：US13156370
申请日：2011-06-09
申请人： Ronald Kakoschke , Harald Seidl
发明人： Ronald Kakoschke , Harald Seidl
IPC分类号： G11C11/00
CPC分类号： H01L21/28282 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/4966
摘要： One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.
摘要翻译：一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述衬底上的栅极堆叠，所述栅极堆叠包括设置在电荷存储层上的控制栅极; 以及设置在所述衬底上并且从所述栅极堆叠横向设置的间隔物选择栅极，所述选择栅极包括碳同素异形体。

9. 发明授权

US08520356B2 Relay controller for defined hold current for a relay 有权
标题翻译：用于继电器定义的保持电流的继电器控制器
公开(公告)号：US08520356B2
公开(公告)日：2013-08-27
申请号：US13232746
申请日：2011-09-14
申请人： Michael Lenz
发明人： Michael Lenz
IPC分类号： H01H9/00
CPC分类号： H01H47/22 , H01H47/32 , H01H2047/025
摘要： The invention relates to a relay controller for controlling an excitation current of a relay, wherein the relay controller is designed, upon the energization of the relay by means of a switch, to control the excitation current through the excitation winding of the relay in such a way that through the excitation winding there flows firstly a pull-in current and, after a pull-in time has elapsed, through the excitation winding there flows a holding current that is lower than the pull-in current, and wherein the relay controller is designed, upon the switching-off of the relay by means of the switch, to feed a commutation current that flows through the excitation winding to the commutation device through the first terminal and through the second terminal of the relay controller.
摘要翻译：本发明涉及一种用于控制继电器的励磁电流的继电器控制器，其中继电器控制器在继电器通过开关通电时设计成通过继电器的励磁绕组来控制励磁电流，通过励磁绕组的方式首先流入引入电流，并且在经过引入时间之后，通过励磁绕组流过低于引入电流的保持电流，并且其中继电器控制器设计在继电器通过开关断开时，将通过励磁绕组流过的换向电流通过第一端子和继电器控制器的第二端子馈送到换向装置。

10. 发明授权

US08508019B2 Capacitor structure 有权
标题翻译：电容结构
公开(公告)号：US08508019B2
公开(公告)日：2013-08-13
申请号：US13541782
申请日：2012-07-05
申请人： Philipp Riess
发明人： Philipp Riess
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L28/60 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.
摘要翻译：一个或多个实施例涉及包括电容器的半导体芯片，所述电容器包括：多个导电板，每个所述板包括设置在所述第一导电条上或之下的第一导电条和第二导电条，所述第二导电每个板的条带基本上平行于同一板的第一导电条，每个板的第二导电条通过至少一个导电通孔电耦合到板的第一导电条，每组的第二导电条至少两个连续的板沿着板的长度方向彼此间隔开。

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