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1. 发明授权

US09177995B2 Vertical interconnect structure, memory device and associated production method 有权
标题翻译：垂直互连结构，存储器件及相关生产方法
公开(公告)号：US09177995B2
公开(公告)日：2015-11-03
申请号：US13591247
申请日：2012-08-22
申请人： Martin Gutsche , Franz Kreupl , Harald Seidl
发明人： Martin Gutsche , Franz Kreupl , Harald Seidl
IPC分类号： H01L27/10 , H01L27/24 , H01L21/285 , H01L27/108 , B82Y10/00 , H01L21/768 , H01L27/22
CPC分类号： H01L27/24 , B82Y10/00 , H01L21/28525 , H01L21/76834 , H01L21/76885 , H01L21/76889 , H01L27/10855 , H01L27/10888 , H01L27/228 , H01L2221/1094
摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
摘要翻译：本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂，随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

2. 发明授权

US08199560B2 Memory device comprising select gate including carbon allotrope 有权
标题翻译：存储器件包括选择栅极，包括碳同素异形体
公开(公告)号：US08199560B2
公开(公告)日：2012-06-12
申请号：US13156370
申请日：2011-06-09
申请人： Ronald Kakoschke , Harald Seidl
发明人： Ronald Kakoschke , Harald Seidl
IPC分类号： G11C11/00
CPC分类号： H01L21/28282 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/4966
摘要： One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.
摘要翻译：一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述衬底上的栅极堆叠，所述栅极堆叠包括设置在电荷存储层上的控制栅极; 以及设置在所述衬底上并且从所述栅极堆叠横向设置的间隔物选择栅极，所述选择栅极包括碳同素异形体。

3. 发明授权

US08188569B2 Phase change random access memory device with transistor, and method for fabricating a memory device 失效
标题翻译：具有晶体管的相变随机存取存储器件以及用于制造存储器件的方法
公开(公告)号：US08188569B2
公开(公告)日：2012-05-29
申请号：US11640065
申请日：2006-12-15
申请人： Harald Seidl
发明人： Harald Seidl
IPC分类号： H01L23/52 , H01L29/00 , G11C11/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”). In one disclosed method, a nanowire of non-conducting material is formed serving as a mould for producing a nanotube of conducting material. A volume of switching active material is deposited on top of the nanotube, so that the ring-shaped front face of the nanotube couples to the switching active material and thus forms a bottom electrode contact.
摘要翻译：本发明涉及一种存储器件，特别涉及一种电阻式切换存储器件，例如相变随机存取存储器（“PCRAM”）。在一种公开的方法中，形成非导电材料的纳米线，用作用于制造导电材料的纳米管的模具。开关活性材料的体积沉积在纳米管的顶部，使得纳米管的环状正面与耦合到开关活性材料并因此形成底部电极接触。

4. 发明授权

US07317201B2 Method of producing a microelectronic electrode structure, and microelectronic electrode structure 有权
标题翻译：微电子电极结构的制造方法和微电子电极结构
公开(公告)号：US07317201B2
公开(公告)日：2008-01-08
申请号：US11296740
申请日：2005-12-07
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.
摘要翻译：在制造微电子电极结构体的方法中，制备第一布线面，设置第一布线面上的绝缘区域，形成绝缘区域的贯通孔，形成通孔内的环状电极，在绝缘区域上形成第二布线平面。环形电极包括第一侧和第二侧，环形电极在第一侧电连接到第一布线平面，并且第二布线平面电连接到环形电极的第二侧。

5. 发明授权

US07273790B2 Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
标题翻译：用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元
公开(公告)号：US07273790B2
公开(公告)日：2007-09-25
申请号：US10901406
申请日：2004-07-27
申请人： Stephan Kudelka , Martin Popp , Harald Seidl , Annette Sänger
发明人： Stephan Kudelka , Martin Popp , Harald Seidl , Annette Sänger
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.
摘要翻译：在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

6. 发明申请

US20060204898A1 Process for producing sublithographic structures 有权
公开(公告)号：US20060204898A1
公开(公告)日：2006-09-14
申请号：US11361849
申请日：2006-02-23
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： G03F7/00
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/30604
摘要： A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures.

7. 发明申请

US20060186480A1 Charge-trapping memory device and method for production 失效
标题翻译：电荷捕获存储器件及其制造方法
公开(公告)号：US20060186480A1
公开(公告)日：2006-08-24
申请号：US11061314
申请日：2005-02-18
申请人： Harald Seidl , Josef Willer , Martin Gutsche
发明人： Harald Seidl , Josef Willer , Martin Gutsche
IPC分类号： H01L31/072 , H01L21/8238
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L29/4234
摘要： A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.
摘要翻译：提供薄SiGe层作为附加的下栅电极层，并且布置在薄栅极氧化物和栅电极层之间，优选多晶硅。 SiGe层可以选择性地蚀刻到栅电极和栅极氧化物，并且在源极/漏极区附近被横向去除以形成凹槽，随后填充适合于电荷捕获的材料。器件结构和制造方法适用于包括存储器单元的本地互连，CMOS逻辑外围和补偿阵列和外围中的层级差异的装置的集成方案。

8. 发明申请

US20060084223A1 Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor 失效
标题翻译：用于制造具有绝缘环和沟槽电容器的沟槽电容器的方法
公开(公告)号：US20060084223A1
公开(公告)日：2006-04-20
申请号：US11205323
申请日：2005-08-17
申请人： Harald Seidl
发明人： Harald Seidl
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10867
摘要： The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate and connected via the buried contact The invention likewise provides a corresponding trench capacitor.
摘要翻译：本发明提供了一种制造具有衬底中的绝缘套环的沟槽电容器的方法，该沟槽电容器在一侧通过埋入触点电连接到衬底，特别是具有平面选择晶体管的半导体存储器单元，该平面选择晶体管设置在该衬底并经由埋入接头连接。本发明同样提供一种对应的沟槽电容器。

9. 发明申请

US20050245027A1 Method for fabricating a stacked capacitor array having a regular arrangement of a plurality of stacked capacitors 有权
公开(公告)号：US20050245027A1
公开(公告)日：2005-11-03
申请号：US11079131
申请日：2005-03-14
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/08 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/10814 , H01L27/10852 , H01L28/82
摘要： The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain second directions (4), comprising the following method steps: provision of an auxiliary layer stack (5) having first auxiliary layers (6) with a predetermined etching rate and at least one second auxiliary layer (7) with a higher etching rate on a substrate (8); etching of in each case one hollow cylinder (9) for each stacked capacitor (2) through the auxiliary layer stack (5) in accordance with the regular arrangement, with the auxiliary layer stack (5) being left in place in intermediate regions (10) between the hollow cylinders (9); isotropic etching of the second auxiliary layers (7) to form widened portions (11) of the hollow cylinders (9), without any second auxiliary layer (7) being left in place between in each case two hollow cylinders (9) which adjoin one another in the first direction (3) and with a second residual auxiliary layer (7a) being left in place between in each case two hollow cylinders (9) which adjoin one another in the second direction (4); conformal deposition of an insulator layer (12) in order to completely fill the widened portions (11); deposition of a first electrode layer (13) in the hollow cylinders (9) in order to form the stacked capacitors (2); filling of the hollow cylinders (9) with a first filling (14); removal of the first auxiliary layers (6), the second residual auxiliary layers (7a) and the first filling (14) and completion of the stacked capacitor array (1).

10. 发明授权

US06949269B2 Method for producing vertical patterned layers made of silicon dioxide 有权
标题翻译：用于生产由二氧化硅制成的垂直图案层的方法
公开(公告)号：US06949269B2
公开(公告)日：2005-09-27
申请号：US10690002
申请日：2003-10-21
申请人： Harald Seidl , Martin Gutsche
发明人： Harald Seidl , Martin Gutsche
IPC分类号： C23C16/02 , C23C16/04 , C23C16/40 , C23C16/44 , C23C16/455 , H01L21/316 , H01L21/334 , H01L21/8242 , B05D1/36
CPC分类号： C23C16/45523 , C23C16/0281 , C23C16/045 , C23C16/402 , H01L21/02164 , H01L21/0228 , H01L21/31612 , H01L27/1087 , H01L29/66181
摘要： A method is taught for fabricating patterned silicon dioxide layers on process areas disposed perpendicularly or at an inclination to a substrate surface. Firstly, a starter layer having leaving groups is produced by non-conformal deposition of a reactive component. Tris(tert-butoxy)silanol is subsequently added. The addition of the tris(tert-butoxy)silanol leads to the formation of a silicon dioxide layer selectively only on the starter layer.
摘要翻译：教导了一种用于在垂直于或者倾斜于衬底表面设置的工艺区域上制造图案化二氧化硅层的方法。首先，通过反应性组分的非共形沉积产生具有离去基团的起始层。随后加入三（叔丁氧基）硅烷醇。三（叔丁氧基）硅烷醇的加入导致仅在引发剂层上形成二氧化硅层。

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