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1. 发明授权

US08338251B2 Method of manufacture transistor with reduced charge carrier mobility 有权
标题翻译：制造具有降低的载流子迁移率的晶体管的方法
公开(公告)号：US08338251B2
公开(公告)日：2012-12-25
申请号：US13472514
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

2. 发明申请

US20110013668A1 SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开
标题翻译：半导体电路布置及相关的温度检测方法
公开(公告)号：US20110013668A1
公开(公告)日：2011-01-20
申请号：US12888528
申请日：2010-09-23
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
IPC分类号： G01K7/01 , H01L29/74 , H01L27/06
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译：公开了半导体电路装置和温度检测方法。一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极实现场效应晶体管。在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层边区。

3. 发明授权

US09197061B2 Electrostatic discharge clamping devices with tracing circuitry 有权
标题翻译：具有跟踪电路的静电放电钳位装置
公开(公告)号：US09197061B2
公开(公告)日：2015-11-24
申请号：US12975210
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
发明人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
IPC分类号： H02H9/00 , H02H9/04 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0285
摘要： Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.
摘要翻译：描述对应于具有跟踪电路的静电放电钳位电路的技术和架构。

4. 发明授权

US08976496B2 Electrostatic discharge blocking circuits 有权
标题翻译：静电放电阻塞电路
公开(公告)号：US08976496B2
公开(公告)日：2015-03-10
申请号：US12975069
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krzysztof Domanski , Klaus von Arnim
发明人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krzysztof Domanski , Klaus von Arnim
IPC分类号： H02H9/04 , H02H3/22 , H02H3/20
CPC分类号： H02H9/046 , H02H3/202 , H02H3/22
摘要： Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.
摘要翻译：描述对应于静电放电阻断电路的技术和架构。

5. 发明授权

US08487380B2 Transistor with reduced charge carrier mobility 有权
标题翻译：具有降低的载流子迁移率的晶体管
公开(公告)号：US08487380B2
公开(公告)日：2013-07-16
申请号：US13472515
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
IPC分类号： H01L27/12
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一个或多个实施例涉及一种装置，包括：第一晶体管，包括鳍片; 以及包括鳍的第二晶体管，所述第一晶体管的鳍具有比所述第二晶体管的鳍更低的载流子迁移率。

6. 发明申请

US20110170337A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20110170337A1
公开(公告)日：2011-07-14
申请号：US13072805
申请日：2011-03-28
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： G11C11/34 , H01L27/12 , H01L21/425
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

7. 发明授权

US07915681B2 Transistor with reduced charge carrier mobility 有权
标题翻译：具有降低的载流子迁移率的晶体管
公开(公告)号：US07915681B2
公开(公告)日：2011-03-29
申请号：US11764500
申请日：2007-06-18
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L27/01
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

8. 发明授权

US07879727B2 Method of fabricating a semiconductor device including a pattern of line segments 有权
标题翻译：制造包括线段图案的半导体器件的方法
公开(公告)号：US07879727B2
公开(公告)日：2011-02-01
申请号：US12354480
申请日：2009-01-15
申请人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
发明人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L21/311
CPC分类号： H01L27/11 , G03F7/40 , G03F7/7035 , H01L21/32139
摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.
摘要翻译：一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有初始宽度。该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

9. 发明申请

US20090209097A1 METHOD OF FORMING INTERCONNECTS 审中-公开
标题翻译：形成互连的方法
公开(公告)号：US20090209097A1
公开(公告)日：2009-08-20
申请号：US12032295
申请日：2008-02-15
申请人： Thomas Schulz , Sergei Postnikov , Hans-Joachim Barth , Klaus von Arnim
发明人： Thomas Schulz , Sergei Postnikov , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/0338 , H01L21/31144
摘要： A method of forming interconnects includes etching a first set of openings in a hard mask using a first photo resist layer with a first pattern of openings as a first etch mask, and etching a second set of openings in the hard mask using a second photo resist layer with a second pattern of openings as a second etch mask. The method includes shrinking the openings in at least one of the first pattern and the second pattern prior to etching the openings in the hard mask.
摘要翻译：一种形成互连的方法包括使用具有第一开口图案的第一光致抗蚀剂层作为第一蚀刻掩模蚀刻在硬掩模中的第一组开口，以及使用第二光致抗蚀剂蚀刻硬掩模中的第二组开口层，其具有作为第二蚀刻掩模的第二开口图案。该方法包括在蚀刻硬掩模中的开口之前收缩第一图案和第二图案中的至少一个中的开口。

10. 发明申请

US20080191282A1 MUGFET ARRAY LAYOUT 有权
标题翻译： MUGFET阵列布局
公开(公告)号：US20080191282A1
公开(公告)日：2008-08-14
申请号：US11674060
申请日：2007-02-12
申请人： Florian Bauer , Klaus Von Arnim
发明人： Florian Bauer , Klaus Von Arnim
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1104 , H01L29/785 , Y10S257/903
摘要： A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the dual fin and single fin transistors.
摘要翻译：电路阵列包括多个单元，其中每个单元具有至少一组奇数的鳍。单元可以布置成包括图案的镜像的重复图案。设置多个翅片形成区域，为双翅片和单翅片晶体管形成翅片。

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