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1. 发明授权

US08338251B2 Method of manufacture transistor with reduced charge carrier mobility 有权
标题翻译：制造具有降低的载流子迁移率的晶体管的方法
公开(公告)号：US08338251B2
公开(公告)日：2012-12-25
申请号：US13472514
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

2. 发明授权

US08487380B2 Transistor with reduced charge carrier mobility 有权
标题翻译：具有降低的载流子迁移率的晶体管
公开(公告)号：US08487380B2
公开(公告)日：2013-07-16
申请号：US13472515
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
IPC分类号： H01L27/12
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一个或多个实施例涉及一种装置，包括：第一晶体管，包括鳍片; 以及包括鳍的第二晶体管，所述第一晶体管的鳍具有比所述第二晶体管的鳍更低的载流子迁移率。

3. 发明申请

US20080283925A1 Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement 审中-公开
标题翻译：多翅片组件布置和制造多鳍组件布置的方法
公开(公告)号：US20080283925A1
公开(公告)日：2008-11-20
申请号：US12124369
申请日：2008-05-21
申请人： Joerg Berthold , Christian Pacha , Klaus Schruefer , Klaus Von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus Schruefer , Klaus Von Arnim
IPC分类号： H01L27/088 , H01L21/82
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/785
摘要： In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another.
摘要翻译：在第一实施例中，多翅片部件布置具有多个多翅片部件部分布置。多片组件部分布置中的每一个具有多个电子部件，该电子部件具有多鳍结构。至少一个多翅片部件部分布置具有至少一个虚拟结构，在形成于至少一个多翅片部件部分布置中的至少两个电子部件之间形成至少一个虚拟结构。虚拟结构形成为使得形成在多翅片部件部分布置中的电子部件的电特性彼此适配。

4. 发明申请

US20110013668A1 SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开
标题翻译：半导体电路布置及相关的温度检测方法
公开(公告)号：US20110013668A1
公开(公告)日：2011-01-20
申请号：US12888528
申请日：2010-09-23
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
IPC分类号： G01K7/01 , H01L29/74 , H01L27/06
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译：公开了半导体电路装置和温度检测方法。一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极实现场效应晶体管。在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层边区。

5. 发明申请

US20120224415A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20120224415A1
公开(公告)日：2012-09-06
申请号：US13472514
申请日：2012-05-16
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： G11C11/412 , H01L21/265
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

6. 发明申请

US20080308850A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20080308850A1
公开(公告)日：2008-12-18
申请号：US11764500
申请日：2007-06-18
申请人： Jorg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jorg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L29/76 , G11C11/34 , H01L21/425
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

7. 发明申请

US20110170337A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20110170337A1
公开(公告)日：2011-07-14
申请号：US13072805
申请日：2011-03-28
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： G11C11/34 , H01L27/12 , H01L21/425
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

8. 发明授权

US07915681B2 Transistor with reduced charge carrier mobility 有权
标题翻译：具有降低的载流子迁移率的晶体管
公开(公告)号：US07915681B2
公开(公告)日：2011-03-29
申请号：US11764500
申请日：2007-06-18
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L27/01
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

9. 发明授权

US07342421B2 CMOS circuit arrangement 有权
标题翻译： CMOS电路布置
公开(公告)号：US07342421B2
公开(公告)日：2008-03-11
申请号：US10573362
申请日：2004-09-17
申请人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
发明人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/01728 , H01L2924/0002 , H03K19/0963 , H01L2924/00
摘要： In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit. At least a portion of the NMOS field effect transistors of the NMOS logic circuit have a first threshold voltage and at least a portion of the PMOS field effect transistors of the PMOS logic circuit have a third threshold voltage. The first clock transistor has a second threshold voltage. The first threshold voltage is lower than the second threshold voltage.
摘要翻译：在本发明的实施例中，提供了一种CMOS电路装置。 CMOS电路装置包括提供具有PMOS场效应晶体管的逻辑功能的PMOS逻辑电路，其中第一工作电位被馈送到PMOS逻辑电路的输入，提供逻辑功能的NMOS逻辑电路，具有NMOS场效应晶体管，第一时钟晶体管，其第一源极/漏极端子耦合到NMOS逻辑电路的输入，其中时钟信号被施加到第一时钟晶体管的栅极端子，并且其中第二工作电位被馈送到第二源极/漏极端子。 PMOS逻辑电路的输出和NMOS逻辑电路的输出彼此耦合。此外，逆变器电路耦合到PMOS逻辑电路的输出端和NMOS逻辑电路的输出。 NMOS逻辑电路的NMOS场效应晶体管的至少一部分具有第一阈值电压，PMOS逻辑电路的PMOS场效应晶体管的至少一部分具有第三阈值电压。第一时钟晶体管具有第二阈值电压。第一阈值电压低于第二阈值电压。

10. 发明申请

US20070284576A1 SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开
标题翻译：半导体电路布置及相关的温度检测方法
公开(公告)号：US20070284576A1
公开(公告)日：2007-12-13
申请号：US11689886
申请日：2007-03-22
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
IPC分类号： H01L25/07 , H01L21/66
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译：公开了半导体电路装置和温度检测方法。一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极实现场效应晶体管。在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层边区。

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