专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06495865B2 Microcathode with integrated extractor 有权
公开(公告)号：US06495865B2
公开(公告)日：2002-12-17
申请号：US09775098
申请日：2001-02-01
申请人： Burgess R. Johnson , Barrett E. Cole , Robert D. Horning , Ulrich Bonne
发明人： Burgess R. Johnson , Barrett E. Cole , Robert D. Horning , Ulrich Bonne
IPC分类号： H01L2974
CPC分类号： H01J3/022
摘要： A microcathode which integrates both an electron emitter, or cathode, and an extractor electrode. The electron emitter is attached to the back side of a thin film microstructure on a first surface of a substrate. Electrons are emitted from the electron emitter and into a via extending through the substrate. An electron beam is formed which is pulled through the via and out of the microcathode by an extractor electrode on a second surface of the substrate. The extractor electrode modulates the electron beam current, defines the beam profile, and accelerates the electrons toward an anode located outside of the microcathode. Microcathode of this invention are particularly suitable as electron emitting devices useful for various types of electron beam utilizing equipment such as flat cathode ray tube displays, microelectronic vacuum tube amplifiers, electron beam exposure devices and the like.

82. 发明授权

US06495863B2 Semiconductor device having diode for input protection circuit of MOS structure device 失效
标题翻译：具有用于MOS结构器件的输入保护电路的二极管的半导体器件
公开(公告)号：US06495863B2
公开(公告)日：2002-12-17
申请号：US09883201
申请日：2001-06-19
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L2974
CPC分类号： H01L29/66106 , H01L24/05 , H01L27/0255 , H01L29/7808 , H01L29/866 , H01L2224/45124 , H01L2924/00014 , H01L2924/12035 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/48
摘要： An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.
摘要翻译：设置在用于布置齐纳二极管的区域上的绝缘体膜具有多个凹槽部分，其连续地布置在形成二极管的每个半导体区域的延伸方向D1上。每个沟槽部分在每个半导体区域的宽度方向D2上延伸，并且具有深度T3。每个半导体区域布置在绝缘膜的上表面上。因此，每个半导体区域具有沿着延伸方向D1布置的多个不规则形状，并且齐纳二极管不仅在横向方向D1上而且在垂直方向D3上具有周长，使得pn结面积在齐纳二极管中增加。因此，为了改善二极管的栅极绝缘膜保护功能，降低了输入保护齐纳二极管的寄生电阻。

83. 发明授权

US06486511B1 Solid state RF switch with high cutoff frequency 有权
标题翻译：具有高截止频率的固态RF开关
公开(公告)号：US06486511B1
公开(公告)日：2002-11-26
申请号：US09942824
申请日：2001-08-30
申请人： Harvey C. Nathanson , Philip C. Smith , R. Chris Clarke , David M. Krafcsik , Lawrence E. Dickens
发明人： Harvey C. Nathanson , Philip C. Smith , R. Chris Clarke , David M. Krafcsik , Lawrence E. Dickens
IPC分类号： H01L2974
CPC分类号： H01L29/66666 , H01L29/435 , H01L29/7827
摘要： A solid state microwave switch having a plurality of adjacent parallel fingers covered with an oxide layer. One end of a finger is an N+ source region while the other end is an N+ drain region, with a current conducting N region between them. The oxide layer is covered with a gate layer to which a gate signal is applied for control of current between the N+ regions through the N region. The gate layer is highly resistive and has a sheet resistance on the order of millions of ohms per square. The length from the source to drain region is around 2 &mgr;m, and the fingers are spaced with a pitch of around 1 &mgr;m.
摘要翻译：一种固态微波开关，具有被氧化物层覆盖的多个相邻的平行指状物。手指的一端是N +源极区域，而另一端是N +漏极区域，它们之间具有导电的N区域。氧化物层被施加栅极信号的栅极层覆盖，以控制通过N区域的N +区域之间的电流。栅极层是高电阻性的，并且具有数百万欧姆/平方的数量级的薄层电阻。从源极到漏极区域的长度约为2μm，并且指状物以约1um的间距间隔开。

84. 发明授权

US06448587B1 Circuit incorporated IGBT and power conversion device using the same 失效
标题翻译：电路并入IGBT和使用其的功率转换器件
公开(公告)号：US06448587B1
公开(公告)日：2002-09-10
申请号：US09985977
申请日：2001-11-07
申请人： Yasuhiko Kohno , Mutsuhiro Mori , Junpei Uruno
发明人： Yasuhiko Kohno , Mutsuhiro Mori , Junpei Uruno
IPC分类号： H01L2974
CPC分类号： H01L29/7395 , H01L27/0623
摘要： A circuit incorporated IGBT is provided with a semiconductor substrate having an IGBT area and a circuit area which are adjacent to each other. In a semiconductor layer of one conductivity type in which a circuit element is formed in the circuit area, there is provided another semiconductor layer of another conductivity type which adjoins the circuit element and has an impurity concentration higher than that of the semiconductor layer of the one conductivity type. An electrode contacts the other semiconductor layer and is connected to an electrode of the IGBT. Carriers are ejected from the other semiconductor layer to the electrode of the IGBT, thereby making it possible to prevent an erroneous operation of the circuit.
摘要翻译：集成IGBT的IGBT设置有具有彼此相邻的IGBT区域和电路区域的半导体衬底。在电路区域中形成有电路元件的一种导电型的半导体层中，提供另一导电类型的另一半导体层，该半导体层与电路元件邻接，杂质浓度高于该半导体层的半导体层导电类型。电极与另一半导体层接触并连接到IGBT的电极。载体从另一半导体层弹出到IGBT的电极，从而可以防止电路的错误操作。

85. 发明授权

US06445012B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06445012B2
公开(公告)日：2002-09-03
申请号：US09862619
申请日：2001-05-23
申请人： Tetsuo Takahashi , Katsumi Nakamura , Tadaharu Minato , Masana Harada
发明人： Tetsuo Takahashi , Katsumi Nakamura , Tadaharu Minato , Masana Harada
IPC分类号： H01L2974
CPC分类号： H01L29/66348 , H01L29/0692 , H01L29/0696 , H01L29/66356 , H01L29/66378 , H01L29/7391 , H01L29/7397 , H01L29/7455 , H01L29/749 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
摘要翻译： pin二极管由p +集电极区，n型缓冲区，n区和n +阴极区形成。从n +阴极区域的表面通过n +阴极区域形成沟槽，到达n-区域。绝缘膜沿沟槽的内壁表面形成。形成与绝缘膜相对的n +阴极区的侧壁相对的栅极电极层。阴极电极形成为与n +阴极区电连接。阳极电极形成为与p +集电极区域电连接。 n +阴极区域完全形成在彼此平行延伸的沟槽之间的表面上。因此，可以获得其中简化了栅极控制电路并且具有良好的性能的功率半导体器件。

86. 发明授权

US06433362B1 Semiconductor device with insulating and transparent original substrate 有权
标题翻译：半导体器件采用绝缘透明原始衬底
公开(公告)号：US06433362B1
公开(公告)日：2002-08-13
申请号：US09509475
申请日：2000-03-28
申请人： J. Pollard
发明人： J. Pollard
IPC分类号： H01L2974
CPC分类号： H01L21/7624 , G02F1/136277 , G02F2001/133302
摘要： The invention concerns an integrated circuit or chip comprising an original support and active and passive microscopic functional elements present in a thin layer made of a monocrystalline semiconductor material. The invention is characterised in that the original support (1) is refractory and transparent, and is coated on one of its surfaces with a thin layer (3) of transparent and insulating inorganic refractory material, said thin layer (3) being itself coated with a thin layer (4) of monocrystalline inorganic semiconductor material, in particular of the silicon or silicon-germanium type, which contains the active functional elements (13-14) and which supports the transparent passive functional elements (15 and 16), other opaque functional elements (17 and 18) being punctually arranged to leave out the transparent cells (12) through which the visible spectrum light can freely pass through the chip entirely.
摘要翻译：本发明涉及一种集成电路或芯片，其包括存在于由单晶半导体材料制成的薄层中的原始支撑和有源和无源微功能元件。本发明的特征在于，原始支撑件（1）是耐火和透明的，并且在其一个表面上涂覆有透明和绝缘的无机耐火材料的薄层（3），所述薄层（3）本身被涂覆单晶无机半导体材料（特别是硅或硅锗型）的薄层（4），其包含活性功能元件（13-14）并且支撑透明无源功能元件（15和16），其它不透明准时布置功能元件（17和18），以留出透明单元（12），可见光谱光可以通过该单元自由地穿过芯片。

87. 发明授权

US06380566B1 Semiconductor device having FET structure with high breakdown voltage 有权
标题翻译：具有具有高击穿电压的FET结构的半导体器件
公开(公告)号：US06380566B1
公开(公告)日：2002-04-30
申请号：US09669737
申请日：2000-09-26
申请人： Tomoko Matsudai , Yusuke Kawaguchi , Kazutoshi Nakamura , Hirofumi Nagano , Akio Nakagawa
发明人： Tomoko Matsudai , Yusuke Kawaguchi , Kazutoshi Nakamura , Hirofumi Nagano , Akio Nakagawa
IPC分类号： H01L2974
CPC分类号： H01L29/7824 , H01L29/0847 , H01L29/7816 , H01L29/7835 , H01L29/78624
摘要： An N-MOSFET is formed on an SOI substrate consisting of a semiconductor substrate, an insulating layer and an n−-active layer. A p-well layer, an n-RESURF layer, and an n-diffusion layer are formed in the surface of the n−-active layer between a source electrode and a drain electrode by means of impurity diffusion. The diffusion regions of the p-well layer and the n-RESURF layer overlap with each other. An end of the n-RESURF layer reaches a position below a gate electrode. The diffusion regions of the p-well layer and the n-diffusion layer do not overlap with each other, so that the n-RESURF layer has a region in direct contact with the n−-active layer between the p-well layer and the n-diffusion layer.
摘要翻译：在由半导体衬底，绝缘层和n-活性层组成的SOI衬底上形成N-MOSFET。通过杂质扩散在源电极和漏电极之间的n-活性层的表面上形成p阱层，n-RESURF层和n扩散层。 p阱层和n-RESURF层的扩散区域彼此重叠。 n-RESURF层的一端到达栅电极下方的位置。 p阱层和n扩散层的扩散区域彼此不重叠，使得n-RESURF层具有与p阱层和p阱层之间的n-活性层直接接触的区域 n扩散层。

88. 发明授权

US06373079B1 Thyristor with breakdown region 有权
标题翻译：晶闸管具有击穿区域
公开(公告)号：US06373079B1
公开(公告)日：2002-04-16
申请号：US09281692
申请日：1999-03-30
申请人： Martin Ruff , Hans-Joachim Schulze
发明人： Martin Ruff , Hans-Joachim Schulze
IPC分类号： H01L2974
CPC分类号： H01L21/263 , H01L29/1016 , H01L29/102 , H01L29/32 , H01L29/7424
摘要： The thyristor is based on a semiconductor body with an anode-side base zone of the first conductivity type and one or more cathode-side base zones of the opposite, second conductivity type. Anode-side and cathode-side emitter zones are provided, and at least one region in the cathode-side base zone whose geometry gives it a reduced breakdown voltage as compared with the remaining regions in the cathode-side base zone and the edge of the semiconductor body. At the anode, below the region of reduced breakdown voltage, the thyristor has at least one recombination zone in which the free charge carriers have a reduced lifetime.
摘要翻译：晶闸管基于具有第一导电类型的阳极侧基极区域和相对的第二导电类型的一个或多个阴极侧基极区域的半导体本体。提供阳极侧和阴极侧发射区，阴极侧基区中的至少一个区域与阴极侧基区中的剩余区域和阴极侧基极区域的边缘相比几何形状具有降低的击穿电压半导体体。在阳极处，在降低的击穿电压的区域之下，晶闸管具有至少一个复合区，其中游离载流子具有降低的寿命。

89. 发明授权

US06316794B1 Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region 有权
标题翻译：具有耐电压区域的保护性氮化硅膜的侧向高电压半导体器件
公开(公告)号：US06316794B1
公开(公告)日：2001-11-13
申请号：US09223668
申请日：1998-12-30
申请人： Masaru Saitou , Gen Tada , Akio Kitamura
发明人： Masaru Saitou , Gen Tada , Akio Kitamura
IPC分类号： H01L2974
CPC分类号： H01L29/408 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.
摘要翻译：提供一种半导体装置，其包括横向高压半导体器件，其包括硅衬底，形成在硅衬底上的一对主电极和形成在硅衬底上的氧化硅膜，使得至少部分氧化硅膜位于主电极之间。半导体器件还包括形成在氧化硅膜上的耐压结构，该结构包括折射率不低于2.8的第一氮化硅膜和形成在第一氮化硅膜上的第二氮化硅膜，并且具有折射率不高于2.2。

90. 发明授权

US06310365B1 Surface voltage sustaining structure for semiconductor devices having floating voltage terminal 有权
标题翻译：具有浮置电压端子的半导体器件的表面电压维持结构
公开(公告)号：US06310365B1
公开(公告)日：2001-10-30
申请号：US09414707
申请日：1999-10-08
申请人： Xingbi Chen
发明人： Xingbi Chen
IPC分类号： H01L2974
CPC分类号： H01L29/0634 , H01L27/0705 , H01L27/088 , H01L29/0615 , H01L29/1095 , H01L29/7816 , H01L29/8611
摘要： A surface voltage sustaining structure for semiconductor device which includes at least one high-side high-voltage device, comprises at least two surface voltage sustaining regions, wherein a first surface voltage sustaining region is for sustaining a voltage drop from a high voltage terminal of the high-side high-voltage device to a floating voltage terminal of the high-side high-voltage device, and a second surface voltage sustaining region is for sustaining a voltage drop from said high voltage terminal or from said floating voltage terminal to the substrate. The potential of the floating-voltage terminal of the high-side high-voltage device can vary (float) from the potential of the substrate up to the potential of the high voltage terminal. By means of the present invention, not only a high-side high-voltage device but also a low-side high-voltage device with a high voltage terminal having potential being the same as the floating voltage terminal and a low voltage terminal having potential being the same as the potential of the substrate, and integrated circuit devices with common terminals having a potential being the same as the floating voltage terminal, as well as integrated circuit devices with common terminals having a potential being the same as the substrate can be implemented simultaneously on a single chip without using dielectric isolation technique or p-n junction isolation technique. The technique of the present invention is technologically compatible to the CMOS or BiCMOS technique.
摘要翻译：一种包括至少一个高侧高压器件的半导体器件的表面电压维持结构，包括至少两个表面电压维持区域，其中第一表面电压维持区域用于维持来自所述高压端子的高压端子的电压降高侧高压装置连接到高侧高压装置的浮动电压端子，第二表面电压维持区域用于维持从所述高压端子或从所述浮动电压端子到基板的电压降。高侧高压器件的浮置电压的电位可以从衬底电位变化（浮动）到高压端子的电位。通过本发明，不仅高边高压器件，而且具有高电压端子的低侧高压器件具有与浮置电压端子相同的电位和具有电位的低电压端子与基板的电位相同，具有与浮置电压端子相同的电位的公共端子的集成电路器件以及具有与基板相同的电位的公共端子的集成电路器件可以同时实现在单芯片上，不使用介质隔离技术或pn结隔离技术。本发明的技术在技术上与CMOS或BiCMOS技术相兼容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式