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81. 发明授权

US06320214B1 Semiconductor device having a ferroelectric TFT and a dummy element 有权
标题翻译：具有铁电TFT和虚拟元件的半导体器件
公开(公告)号：US06320214B1
公开(公告)日：2001-11-20
申请号：US09209214
申请日：1998-12-11
申请人： Akihiro Matsuda , Yoshihisa Nagano , Yasuhiro Uemoto
发明人： Akihiro Matsuda , Yoshihisa Nagano , Yasuhiro Uemoto
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &mgr;m to 14 &mgr;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.
摘要翻译：本发明提供一种包括半导体元件和与半导体元件相邻的虚设半导体元件的半导体器件。当半导体元件是包括底部电极，顶部电极和电极之间的电介质层的电容器元件时，虚拟电容器元件在虚拟电极之间也具有虚拟电极和虚设电介质层。虚拟电极被定位成使得电容器元件的顶部电极和虚拟顶部电极之间的空间处于预定范围（例如，0.3μm至14μm）。由于在干蚀刻工艺中蚀刻离子与电容器电介质层的碰撞被抑制，因此虚拟电容器元件防止电容器介电层降解。

82. 发明授权

US06174822B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06174822B1
公开(公告)日：2001-01-16
申请号：US09175250
申请日：1998-10-20
申请人： Yoshihisa Nagano , Toshie Kutsunai , Yuji Judai , Yasuhiro Uemoto , Eiji Fujii
发明人： Yoshihisa Nagano , Toshie Kutsunai , Yuji Judai , Yasuhiro Uemoto , Eiji Fujii
IPC分类号： H01L2131
CPC分类号： H01L27/1085 , H01L21/76895 , H01L23/5223 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
摘要翻译：半导体器件包括：设置在其上具有集成电路的支撑衬底上并包括下电极，电介质膜和上电极的电容器; 设置为覆盖电容器的第一层间绝缘膜; 选择性地设置在所述第一层间绝缘膜上并通过形成在所述第一层间绝缘膜中的第一接触孔与所述集成电路和所述电容器电连接的第一互连; 由臭氧TEOS形成的第二层间绝缘膜，并设置为覆盖第一互连; 选择性地设置在第二层间绝缘膜上并通过形成在第二层间绝缘膜中的第二接触孔电连接到第一互连的第二互连; 以及设置成覆盖第二互连的钝化层。

83. 发明授权

US06143597A Method of manufacturing capacitor included in semiconductor device and the capacitor thereof 失效
标题翻译：包括在半导体器件中的电容器的制造方法及其电容器
公开(公告)号：US06143597A
公开(公告)日：2000-11-07
申请号：US678866
申请日：1996-07-12
申请人： Akihiro Matsuda , Yoshihisa Nagano , Toru Nasu , Koji Arita , Yasuhiro Uemoto
发明人： Akihiro Matsuda , Yoshihisa Nagano , Toru Nasu , Koji Arita , Yasuhiro Uemoto
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L21/108
CPC分类号： H01L28/56
摘要： A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.
摘要翻译：一种制造电容器的方法包括在第一电极上形成由铁电材料或具有高介电常数的介电材料构成的第一介电层的步骤，烧结第一介电层的步骤，形成第二介电层的步骤第一电介质层，以及在第二电介质层上形成第二电极的步骤。通过在具有大晶粒尺寸的第一电介质层上形成具有小晶粒尺寸的第二电介质层，电容器绝缘层的表面变平。

84. 发明授权

US5245452A Active matric drive liquid crystal display device using polycrystalline silicon pixel electrodes 失效
标题翻译：有源矩阵驱动液晶显示器件使用多晶硅像素电极
公开(公告)号：US5245452A
公开(公告)日：1993-09-14
申请号：US369476
申请日：1989-06-21
申请人： Akira Nakamura , Kohji Senda , Eiji Fujii , Fumiaki Emoto , Yasuhiro Uemoto , Atsuya Yamamoto , Kazunori Kobayashi
发明人： Akira Nakamura , Kohji Senda , Eiji Fujii , Fumiaki Emoto , Yasuhiro Uemoto , Atsuya Yamamoto , Kazunori Kobayashi
IPC分类号： G02F1/1337 , C08F220/54 , G02F1/1343 , G02F1/136 , G02F1/1368 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： G02F1/1368 , C08F220/54 , G02F1/13439 , G02F2202/104
摘要： An image display device includes thin film transistors and pixel electrodes arranged in matrix form on a substrate. A semiconductor layer forming a channel region of the thin film transistor also serves as the pixel electrode, thereby making the structure of the device simple and facilitating fabrication thereof.

85. 发明授权

US08497553B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08497553B2
公开(公告)日：2013-07-30
申请号：US12905801
申请日：2010-10-15
申请人： Hiroto Yamagiwa , Shingo Hashizume , Ayanori Ikoshi , Manabu Yanagihara , Yasuhiro Uemoto
发明人： Hiroto Yamagiwa , Shingo Hashizume , Ayanori Ikoshi , Manabu Yanagihara , Yasuhiro Uemoto
IPC分类号： H01L23/62 , H01L29/66 , H01L31/06 , H01L21/338 , H02H3/00 , H02H9/02
CPC分类号： H01L29/7786 , H01L27/0266 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/41758 , H01L29/42364 , H01L29/8124 , H01L29/861
摘要： A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.
摘要翻译：半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和第二保护元件欧姆电极。第二元件区域的面积小于第一元件区域。

86. 再颁专利

USRE41625E1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：USRE41625E1
公开(公告)日：2010-09-07
申请号：US10829476
申请日：2004-04-22
申请人： Yoshihisa Nagano , Yasuhiro Uemoto
发明人： Yoshihisa Nagano , Yasuhiro Uemoto
IPC分类号： H01L29/94
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/11507 , H01L27/11509 , H01L28/55
摘要： A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.
摘要翻译：保护绝缘膜沉积在形成在半导体衬底上的第一和第二场效应晶体管上。在保护绝缘膜上形成由电容器下电极构成的电容器，由绝缘金属氧化物膜构成的电容绝缘膜和电容器上电极。形成在保护绝缘膜中的第一接触插塞提供电容器下电极和第一场效应晶体管的杂质扩散层之间的直接连接。形成在保护绝缘膜中的第二接触插塞提供电容器上电极和第二场效应晶体管的杂质扩散层之间的直接连接。

87. 发明申请

US20100207164A1 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20100207164A1
公开(公告)日：2010-08-19
申请号：US12682007
申请日：2009-08-07
申请人： Daisuke Shibata , Tatsuo Morita , Yasuhiro Uemoto
发明人： Daisuke Shibata , Tatsuo Morita , Yasuhiro Uemoto
IPC分类号： H01L29/772
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/1075 , H01L29/2003 , H01L29/41766
摘要： A field effect transistor includes a first nitride semiconductor layer 13 and a second nitride semiconductor layer 14 having a band gap larger than that of the first nitride semiconductor layer 13 which are formed in this order in an upward direction on a conductive substrate 11, a source electrode 15 and a drain electrode 16 which are electrically connected to a two-dimensional electron gas layer 21, and a gate electrode 18. A rise voltage of a drain-substrate current is lower than a rise voltage of a drain-gate current and a rise voltage of a drain-source current.
摘要翻译：场效应晶体管包括第一氮化物半导体层13和具有大于第一氮化物半导体层13的带隙的第二氮化物半导体层14，该第二氮化物半导体层14在导电基板11上沿向上方向依次形成，源极与二维电子气体层21电连接的电极15和漏电极16以及栅极电极18.漏极 - 基板电流的上升电压低于漏极 - 栅极电流的上升电压，并且漏 - 源电流的上升电压。

88. 再颁专利

USRE40602E1 Semiconductor device having a ferroelectric TFT and a dummy element 有权
标题翻译：具有铁电TFT和虚拟元件的半导体器件
公开(公告)号：USRE40602E1
公开(公告)日：2008-12-09
申请号：US10611307
申请日：2003-07-01
申请人： Akihiro Matsuda , Yoshihisa Nagano , Yasuhiro Uemoto
发明人： Akihiro Matsuda , Yoshihisa Nagano , Yasuhiro Uemoto
IPC分类号： H01L21/70
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 μm to 14 μm). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collisions of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.
摘要翻译：本发明提供一种包括半导体元件和与半导体元件相邻的虚设半导体元件的半导体器件。当半导体元件是包括底部电极，顶部电极和电极之间的电介质层的电容器元件时，虚拟电容器元件在虚拟电极之间也具有虚拟电极和虚设电介质层。虚拟电极被定位成使得电容器元件的顶部电极和虚拟顶部电极之间的空间处于预定范围（例如，0.3μm至14μm）。由于在干式蚀刻工艺中蚀刻离子与电容器电介质层的碰撞被抑制，所以虚拟电容器元件防止电容器介电层降解。

89. 发明申请

US20050082638A1 Semiconductor device and method for fabricating the same 审中-公开
公开(公告)号：US20050082638A1
公开(公告)日：2005-04-21
申请号：US10968623
申请日：2004-10-19
申请人： Yoshihisa Nagano , Toshie Kutsunai , Yuji Judai , Yasuhiro Uemoto , Eiji Fujii
发明人： Yoshihisa Nagano , Toshie Kutsunai , Yuji Judai , Yasuhiro Uemoto , Eiji Fujii
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L29/76 , H01L21/3205
CPC分类号： H01L27/1085 , H01L21/76895 , H01L23/5223 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

90. 发明授权

US06573111B2 Method of making a semiconductor device with capacitor element 失效
公开(公告)号：US06573111B2
公开(公告)日：2003-06-03
申请号：US10177781
申请日：2002-06-20
申请人： Yoshihisa Nagano , Yasuhiro Uemoto , Yuji Judai , Masamichi Azuma , Eiji Fujii
发明人： Yoshihisa Nagano , Yasuhiro Uemoto , Yuji Judai , Masamichi Azuma , Eiji Fujii
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/76895 , H01L27/11507
摘要： A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive material other than titanium.

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