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81. 发明授权

US07022621B1 Iridium oxide nanostructure patterning 有权
标题翻译：氧化铱纳米结构图案
公开(公告)号：US07022621B1
公开(公告)日：2006-04-04
申请号：US11013804
申请日：2004-12-15
申请人： Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff , Sheng Teng Hsu
发明人： Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff , Sheng Teng Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/31111 , B81C1/00111 , B82Y10/00
摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
摘要翻译：提供了用于构图氧化铱（IrOx）纳米结构的方法。该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。例如，第一种材料可以是难熔金属或难熔金属氧化物。第二种材料可以是SiOx。选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

82. 发明授权

US07015147B2 Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer 失效
标题翻译：使用Si1-xGex层的选择性蚀刻制造无硅（SON）MOSFET制造
公开(公告)号：US07015147B2
公开(公告)日：2006-03-21
申请号：US10625065
申请日：2003-07-22
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L29/66772 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78639 , H01L29/78654
摘要： A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1−xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1−xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1−xGex layer; trench etching of the top silicon and Si1−xGex, into the silicon substrate to form a first trench; selectively etching the Si1−xGex layer to remove substantially all of the Si1−xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1−xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.
摘要翻译：使用Si 1-x Ge层的选择性蚀刻制造无硅无硅（SON）MOSFET的方法包括制备硅衬底; 在硅衬底上生长外延Si 1-x Ge层x层; 在外延Si 1-x Ge层上生长外延薄顶硅层; 将硅和Si 1-x N x X x x沟槽蚀刻到硅衬底中以形成第一沟槽; 选择性地蚀刻Si 1-x Ge Ge层，以便基本上除去所有的Si 1-x N x Ge x Si 形成气隙; 通过CVD沉积SiO 2层以填充第一沟槽; 从第二沟槽进行沟槽蚀刻; 选择性地蚀刻剩余的Si 1-x N Ge x层; 通过CVD沉积SiO 2的第二层以填充第二沟槽，从而使源极，漏极和沟道与衬底去耦合; 并通过最先进的CMOS制造技术完成结构。

83. 发明授权

US06899858B2 Method of synthesis of hafnium nitrate for HfO2 thin film deposition via ALCVD process 失效
标题翻译：通过ALCVD法合成HfO2薄膜沉积硝酸铪的方法
公开(公告)号：US06899858B2
公开(公告)日：2005-05-31
申请号：US10350641
申请日：2003-01-23
申请人： Wei-Wei Zhuang , David R. Evans , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Sheng Teng Hsu
IPC分类号： C01G27/00 , C01G27/02 , C23C16/40 , H01L21/316 , C01B21/48
CPC分类号： C01G27/00 , C01G27/02
摘要： A method of preparing a hafnium nitrate thin film includes placing phosphorus pentoxide in a first vessel; connecting the first vessel to a second vessel containing hafnium tetrachloride; cooling the second vessel with liquid nitrogen; dropping fuming nitric acid into the first vessel producing N2O5 gas; allowing the N2O5 gas to enter the second vessel; heating the first vessel until the reaction is substantially complete; disconnecting the two vessels; removing the second vessel from the liquid nitrogen bath; heating the second vessel; refluxing the contents of the second vessel; drying the compound in the second vessel by dynamic pumping; purifying the compound in the second vessel by sublimation to form Hf(NO3)4, and heating the Hf(NO3)4 to produce HfO2 for use in an ALCVD process.
摘要翻译：制备硝酸铪薄膜的方法包括将五氧化二磷放置在第一容器中; 将第一容器连接到含有四氯化铪的第二容器; 用液氮冷却第二个容器; 将发烟硝酸滴入产生N 2 O 5气体的第一容器中; 允许N 2 O 5气体进入第二容器; 加热第一个容器直到反应基本完成; 断开两艘船舶; 从液氮浴中除去第二容器; 加热第二艘船; 回流第二容器的内容物; 通过动态泵送干燥第二容器中的化合物; 通过升华纯化第二容器中的化合物以形成Hf（NO 3 N 3）4，并加热Hf（NO 3 N 3）3 4生产用于ALCVD工艺的HfO 2 2。

84. 发明授权

US06897530B2 Ultra-thin SOI MOS transistors 失效
标题翻译：超薄SOI MOS晶体管
公开(公告)号：US06897530B2
公开(公告)日：2005-05-24
申请号：US10261447
申请日：2002-09-30
申请人： Sheng Teng Hsu
发明人： Sheng Teng Hsu
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： H01L27/1203 , H01L21/84
摘要： A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a distance from said main gate active region of about 200 nm. A method of forming an ultra-thin SOI MOS transistor includes preparing a silicon wafer, including forming a top silicon layer having a thickness of between about 100 nm to 200 nm, thinning the top silicon layer to a thickness of between about 10 nm to 30 nm, and forming an oxide layer over the top silicon layer; forming a layer of material taken from the group of material consisting of polysilicon and silicide; forming an oxide cap on the formed layer of material, and etching the oxide cap and layer of material to form a main gate electrode and an auxiliary gate electrode on either side thereof; forming an oxide layer over the structure and etching the oxide layer to form sidewall oxide structures about the gate electrodes; depositing a layer of material taken from the group of material consisting of polysilicon, silicide and metal, etching the newly deposited layer of material, and metallizing the structure.
摘要翻译：晶体管结构包括厚度小于或等于30nm的主栅极硅有源区; 以及位于所述主栅极硅有源区两侧的辅助栅极有源区，所述辅助栅极有源区与所述主栅极有源区间隔开约200nm的距离。形成超薄SOI MOS晶体管的方法包括制备硅晶片，其包括形成厚度在约100nm至200nm之间的顶部硅层，将顶部硅层变薄至约10nm至30nm的厚度并且在顶部硅层上形成氧化物层; 形成从由多晶硅和硅化物组成的材料组中取出的材料层; 在所形成的材料层上形成氧化物盖，蚀刻氧化物盖和材料层，以在其两侧形成主栅电极和辅助栅电极; 在所述结构上形成氧化物层并蚀刻所述氧化物层以形成围绕所述栅电极的侧壁氧化物结构; 沉积从由多晶硅，硅化物和金属组成的材料组中取出的材料层，蚀刻新沉积的材料层，并对结构进行金属化。

85. 发明授权

US06897074B1 Method for making single-phase c-axis doped PGO ferroelectric thin films 失效
标题翻译：制备单相c轴掺杂PGO铁电薄膜的方法
公开(公告)号：US06897074B1
公开(公告)日：2005-05-24
申请号：US10794736
申请日：2004-03-03
申请人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/316 , H01L41/22
CPC分类号： H01L21/31691 , H01L28/55 , H01L41/317
摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
摘要翻译：描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

86. 发明授权

US06858905B2 Methods of manufacturing low cross-talk electrically programmable resistance cross point memory structures 有权
标题翻译：制造低串扰电可编程电阻交叉点存储器结构的方法
公开(公告)号：US06858905B2
公开(公告)日：2005-02-22
申请号：US10713327
申请日：2003-11-13
申请人： Sheng Teng Hsu , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang
IPC分类号： H01L27/115 , G11C11/00 , G11C11/15 , G11C11/56 , G11C13/00 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/24 , H01L43/08 , H01L21/20
CPC分类号： H01L27/24 , G11C11/15 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77
摘要： Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.
摘要翻译：提供了低串扰电阻交叉点存储器件，以及制造和使用方法。存储装置包括使用插入在上电极和下电极的交叉点处的钙钛矿材料形成的钻头。每个位具有响应于施加一个或多个电压脉冲而可以在一定范围内的值改变的电阻率。可以使用电压脉冲来增加比特的电阻率，降低比特的电阻率，或者确定比特的电阻率。提供存储器电路以帮助编程和读出位区域。

87. 发明授权

US06833572B2 Electrode materials with improved hydrogen degradation resistance 失效
标题翻译：具有改善耐氢降解性的电极材料
公开(公告)号：US06833572B2
公开(公告)日：2004-12-21
申请号：US10229603
申请日：2002-08-27
申请人： Fengyan Zhang , Tingkai Li , Hong Ying , Yoshi Ono , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Hong Ying , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L21/31604 , H01L21/31683 , H01L28/55
摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
摘要翻译：用于铁电体器件的电极包括底部电极; 铁电层以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

88. 发明授权

US06825086B2 Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner 失效
标题翻译：应变硅沟道CMOS与牺牲浅沟槽隔离氧化物衬垫
公开(公告)号：US06825086B2
公开(公告)日：2004-11-30
申请号：US10345728
申请日：2003-01-17
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807
摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.
摘要翻译：已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

89. 发明授权

US06699764B1 Method for amorphization re-crystallization of Si1-xGex films on silicon substrates 失效
标题翻译：硅衬底上Si1-xGex薄膜的非晶化再结晶方法
公开(公告)号：US06699764B1
公开(公告)日：2004-03-02
申请号：US10238146
申请日：2002-09-09
申请人： Douglas J. Tweet , Jer-shen Maa , Jong-Jan Lee , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jer-shen Maa , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/263 , C30B1/023 , C30B1/04 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02694 , H01L29/1054 , H01L29/165 , Y10S438/933
摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.
摘要翻译：在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在Si1-XGeX层上外延生长硅帽; 通过Si1-XGeX层将氢离子注入Si1-XGeX / Si界面以下约3nm至100nm之间的深度; 将Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

90. 发明授权

US06537361B2 Method of the synthesis and control of PGO spin-coating precursor solutions 失效
公开(公告)号：US06537361B2
公开(公告)日：2003-03-25
申请号：US09822637
申请日：2001-03-30
申请人： Wei-Wei Zhuang , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L2122
CPC分类号： H01L21/02197 , C01G21/00 , C01P2002/86 , H01L21/02112 , H01L21/02175 , H01L21/02282 , H01L21/31604 , H01L21/31691
摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

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