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1. 发明授权

US08951842B2 Semiconductor growth substrates and associated systems and methods for die singulation 有权
标题翻译：半导体生长衬底及相关系统和模具分离方法
公开(公告)号：US08951842B2
公开(公告)日：2015-02-10
申请号：US13349432
申请日：2012-01-12
申请人： Xiaolong Fang , Lifang Xu , Tingkai Li , Thomas Gehrke
发明人： Xiaolong Fang , Lifang Xu , Tingkai Li , Thomas Gehrke
IPC分类号： H01L33/50 , H01L33/48 , H01L21/66 , H01L23/544 , H01L33/00 , H01L21/78
CPC分类号： H01L33/32 , H01L21/78 , H01L22/10 , H01L22/32 , H01L22/34 , H01L23/544 , H01L33/0066 , H01L33/007 , H01L33/0095 , H01L33/48 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.
摘要翻译：公开了半导体生长衬底和用于芯片分离的相关系统和方法。用于制造半导体器件的代表性方法包括在位于衬底材料的相邻器件生长区域之间的切割街道上形成间隔开的结构。该方法还可以包括通过将半导体材料的第一部分添加到器件生长区域并将半导体材料的第二部分添加到该结构体来外延生长半导体材料。该方法还可以进一步包括在器件生长区域处形成半导体器件，并且在切割街道处通过在切割街道处去除间隔开的结构和下面的衬底材料来将半导体器件彼此分离。

2. 发明申请

US20130181219A1 SEMICONDUCTOR GROWTH SUBSTRATES AND ASSOCIATED SYSTEMS AND METHODS FOR DIE SINGULATION 有权
公开(公告)号：US20130181219A1
公开(公告)日：2013-07-18
申请号：US13349432
申请日：2012-01-12
申请人： Xiaolong Fang , Lifang Xu , Tingkai Li , Thomas Gehrke
发明人： Xiaolong Fang , Lifang Xu , Tingkai Li , Thomas Gehrke
IPC分类号： H01L33/48
CPC分类号： H01L33/32 , H01L21/78 , H01L22/10 , H01L22/32 , H01L22/34 , H01L23/544 , H01L33/0066 , H01L33/007 , H01L33/0095 , H01L33/48 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

3. 发明授权

US07723729B2 Compound semiconductor-on-silicon wafer with a silicon nanowire buffer layer 有权
标题翻译：具有硅纳米线缓冲层的复合半导体硅片
公开(公告)号：US07723729B2
公开(公告)日：2010-05-25
申请号：US12036396
申请日：2008-02-25
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L31/0312 , H01L29/20 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/02433 , H01L21/02447 , H01L21/0245 , H01L21/02502 , H01L21/0254 , H01L21/02546 , H01L21/02639 , H01L21/0265 , H01L29/045 , H01L29/0673
摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.
摘要翻译：提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。该方法形成Si衬底。在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。化合物半导体选择性沉积在Si纳米线尖端上。横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。化合物半导体可以是GaN，GaAs，GaAlN或SiC。在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

4. 发明授权

US07633108B2 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US07633108B2
公开(公告)日：2009-12-15
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Teng Hsu , Wei-Wei Zhuang , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , Wei-Wei Zhuang , David R. Evans
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method provides a substrate; forms an MSM bottom electrode overlying the substrate; forms a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forms an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法提供基底; 形成覆盖衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnOx半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

5. 发明授权

US07625595B2 Method of monitoring PCMO precursor synthesis 有权
标题翻译：监测PCMO前体合成的方法
公开(公告)号：US07625595B2
公开(公告)日：2009-12-01
申请号：US11403022
申请日：2006-04-11
申请人： Wei-Wei Zhuang , David R. Evans , Tingkai Li , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Tingkai Li , Sheng Teng Hsu
IPC分类号： B05D5/12
CPC分类号： H01L22/20 , H01L21/31691 , H01L22/14
摘要： A method of monitoring synthesis of PCMO precursor solutions includes preparing a PCMO precursor solution and withdrawing samples of the precursor solution at intervals during a reaction phase of the PCMO precursor solution synthesis. The samples of the PCMO precursor solution are analyzed by UV spectroscopy to determine UV transmissivity of the samples of the PCMO precursor solution and the samples used to form PCMO thin films. Electrical characteristics of the PCMO thin films formed from the samples are determined to identify PCMO thin films having optimal electrical characteristics. The UV spectral characteristics of the PCMO precursor solutions are correlated with the PCMO thin films having optimal electrical characteristics. The UV spectral characteristics are used to monitor synthesis of future batches of the PCMO precursor solutions, which will result in PCMO thin films having optimal electrical characteristics.
摘要翻译：监测PCMO前体溶液合成的方法包括制备PCMO前体溶液，并在PCMO前体溶液合成反应期间间隔取出前体溶液样品。通过紫外光谱分析PCMO前体溶液的样品，以确定PCMO前体溶液和用于形成PCMO薄膜的样品的UV透射率。确定由样品形成的PCMO薄膜的电特性以鉴定具有最佳电特性的PCMO薄膜。 PCMO前体溶液的UV光谱特性与具有最佳电学特性的PCMO薄膜相关。 UV光谱特性用于监测未来批次的PCMO前体溶液的合成，这将导致具有最佳电特性的PCMO薄膜。

6. 发明申请

US20080171424A1 Epitaxial growth of GaN and SiC on silicon using nanowires and nanosize nucleus methodologies 审中-公开
标题翻译：使用纳米线和纳米尺度核方法在硅上外延生长GaN和SiC
公开(公告)号：US20080171424A1
公开(公告)日：2008-07-17
申请号：US11653802
申请日：2007-01-16
申请人： Tingkai Li , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Tingkai Li , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L21/205
CPC分类号： H01L21/02513 , H01L21/02381 , H01L21/0245 , H01L21/02529 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L21/0265
摘要： A method of fabricating a continuous layer of a defect sensitive material on a silicon substrate includes preparing a silicon substrate; forming a nanostructure array directly on the silicon substrate; depositing a selective growth enhancing layer on the substrate; smoothing the selective growth enhancing layer; and growing a continuous layer of the defect sensitive material on the nanostructure array.
摘要翻译：在硅衬底上制造缺陷敏感材料的连续层的方法包括制备硅衬底; 在硅衬底上直接形成纳米结构阵列; 在衬底上沉积选择性生长增强层; 平滑选择性生长增强层; 并在纳米结构阵列上生长不连续的缺陷敏感材料层。

7. 发明申请

US20080164569A1 Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same 有权
标题翻译：铽掺杂，富硅氧化物电致发光器件及其制造方法
公开(公告)号：US20080164569A1
公开(公告)日：2008-07-10
申请号：US11582275
申请日：2006-10-16
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L29/00
CPC分类号： H01L27/15 , H01L33/0004 , H01L33/343
摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.
摘要翻译：一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

8. 发明授权

US07358160B2 Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer 有权
标题翻译：用硅纳米线缓冲层选择性形成硅化合物半导体晶片的方法
公开(公告)号：US07358160B2
公开(公告)日：2008-04-15
申请号：US11481437
申请日：2006-07-06
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/36
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02529 , H01L21/02538 , H01L21/7624
摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where X≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.
摘要翻译：提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。该方法形成Si衬底。在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。化合物半导体选择性沉积在Si纳米线尖端上。横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或Si X N Y ，其中 X <= 3 AND Y <= 4。化合物半导体可以是GaN，GaAs，GaAlN或SiC。在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。

9. 发明申请

US20070284575A1 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US20070284575A1
公开(公告)日：2007-12-13
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L29/12
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

10. 发明授权

US07297602B2 Conductive metal oxide gate ferroelectric memory transistor 失效
标题翻译：导电金属氧化物栅极铁电存储晶体管
公开(公告)号：US07297602B2
公开(公告)日：2007-11-20
申请号：US10659547
申请日：2003-09-09
申请人： Sheng Teng Hsu , Tingkai Li
发明人： Sheng Teng Hsu , Tingkai Li
IPC分类号： H01L21/331 , H01L21/335
CPC分类号： G11C11/22 , H01L21/28273 , H01L21/28291 , H01L29/66545 , H01L29/66553 , H01L29/66825 , H01L29/6684 , H01L29/78391
摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.
摘要翻译：本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

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