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81. 发明申请

US20080315911A1 Receiver circuit 有权
标题翻译：接收电路
公开(公告)号：US20080315911A1
公开(公告)日：2008-12-25
申请号：US12081154
申请日：2008-04-11
申请人： Tsuyoshi Ebuchi , Toru Iwata , Takefumi Yoshikawa
发明人： Tsuyoshi Ebuchi , Toru Iwata , Takefumi Yoshikawa
IPC分类号： H03K19/007
CPC分类号： H04L25/493
摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
摘要翻译：在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

82. 发明授权

US07453313B2 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US07453313B2
公开(公告)日：2008-11-18
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： G06F3/02
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

83. 发明申请

US20060178790A1 High-altitude capable wide velocity range flight velocity vector measurement probe and measurement system 有权
公开(公告)号：US20060178790A1
公开(公告)日：2006-08-10
申请号：US11224030
申请日：2005-09-13
申请人： Masashi Shigemi , Akira Koike , Makoto Ueno , Tomonari Hirotani , Teruomi Nakaya , Hiroshi Wakai , Toru Iwata
发明人： Masashi Shigemi , Akira Koike , Makoto Ueno , Tomonari Hirotani , Teruomi Nakaya , Hiroshi Wakai , Toru Iwata
IPC分类号： G01C23/00
CPC分类号： G01P5/175 , G01C5/005 , G01P5/16 , G01P13/025
摘要： It is an object of the present invention to solve the problem of a drop in precision in conventional systems using a square pyramid type five-hole probe due to the drop in atmospheric pressure in high altitude ranges, and to provide a wide velocity range flight velocity vector measurement system that can prevent a drop in measurement precision. Furthermore, it is also an object of the present invention to provide a method for eliminating the effects of detection fluctuations caused by adhering water droplets, ice particles or dust in a wide velocity range flight velocity vector measurement system. The flight velocity vector measurement probe of the present invention comprises means in which a static pressure hole is formed in the tube wall surface of the probe, so that a static pressure value is obtained from the pressure detected by this static pressure hole, the Mach number M is calculated on the basis of an equation approximated by a fourth-order polynomial of the static pressure/total pressure signal and the angle of attack, and in cases where an abnormal detection value is detected, this is replaced by the preceding detection value.

84. 发明申请

US20060176091A1 Delay locked loop circuit 审中-公开
标题翻译：延时锁定回路电路
公开(公告)号：US20060176091A1
公开(公告)日：2006-08-10
申请号：US11289753
申请日：2005-11-30
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

85. 发明申请

US20060010901A1 Indoor apparatus for air conditioner 有权
标题翻译：空调室内机
公开(公告)号：US20060010901A1
公开(公告)日：2006-01-19
申请号：US10533200
申请日：2003-10-30
申请人： Toru Iwata , Masakazu Hirai
发明人： Toru Iwata , Masakazu Hirai
IPC分类号： F25D17/06
CPC分类号： F24F1/0007 , F24F1/0011 , F24F1/0022 , F24F2001/0037
摘要： An air discharge outlet comprises line air discharge outlets (35) and corner air discharge outlets (36). The line air discharge outlets (35) are so formed as to extend, respectively, along four sides of a casing bottom part having four side parts and four corner parts wherein the side and corner parts are formed in contiguous relationship to one another. The corner air discharge outlets (36) are formed, respectively, in the four casing corner parts so that each corner air discharge outlet (36) establishes connection between adjacent ones of the line air discharge outlets (35). And, each line air discharge outlet (35) is provided with a swing vane (38) swingable about a longitudinal shaft (41) of each line air discharge outlet (35). Each corner air discharge outlet (36) is provided with a fixed stationary vane (39).
摘要翻译：空气排出口包括排气出口（35）和角空气排出口（36）。线排出口35形成为分别沿着具有四个侧面部分和四个拐角部分的壳体底部的四个侧面延伸，其中侧部和拐角部分彼此连续地形成。角空气排出口36分别形成在四个壳体角部，使得每个角空气排出口36建立相邻的排气出口35之间的连接。并且，每排排气口（35）设置有可围绕每排排气口（35）的纵轴（41）摆动的摆动叶片（38）。每个角空气排出口（36）设置有固定静止叶片（39）。

86. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

87. 发明授权

US06853223B2 Phase comparator and clock recovery circuit 有权
标题翻译：相位比较器和时钟恢复电路
公开(公告)号：US06853223B2
公开(公告)日：2005-02-08
申请号：US10345994
申请日：2003-01-17
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Toru Iwata
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Toru Iwata
IPC分类号： H03K5/26 , H03D13/00 , H03L7/08 , H03L7/087 , H03L7/089 , H04L7/033 , H03L7/06
CPC分类号： H03D13/004 , H04L7/033
摘要： The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.
摘要翻译：本发明的目的在于提供一种相位比较器和时钟恢复电路，适用于支持高速比特速率为每秒千兆位的数据信号的应用。相位比较器分别接收从数据信号RD / NRD产生的分频信号NHOLDH和NHOLDL，并间歇地执行信号dDAT和信号CLK之间的相位比较。这增加了相位比较的定时裕度，并且可以对高速比特率信号执行相位比较。提供用作时钟恢复电路的相位比较器使得可以以高达1吉比特每秒的高速比特率来处理数据信号。

88. 发明授权

US06809953B2 Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof 有权
标题翻译：电位发生电路，电位产生装置及使用其的半导体装置及其驱动方法
公开(公告)号：US06809953B2
公开(公告)日：2004-10-26
申请号：US10440277
申请日：2003-05-16
申请人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
发明人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
IPC分类号： G11C1122
CPC分类号： H02M3/07 , H02M3/073
摘要： A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through fourth periods are repeated.
摘要翻译：电位发生电路包括电容器（4）; 与电容器（4）串联连接的铁电电容器（6）。输出端子（11）; 用于使输出端子（11）接地的电容器（10）; 用于将两个电容器（4,6）之间的连接节点（5）连接到输出端子（11）的开关（9）; 和用于将连接节点（5）连接到地面的开关（1）; 其中在第一时段期间，当开关（1）和（9）处于断开状态时，端子（3）被提供有正电位并且端子（7）接地; 其中在所述第一周期之后的第二时段期间，所述端子（3）接地，并且所述开关（9）处于接通状态; 其中在所述第二时段之后的第三时段期间，所述开关（9）处于断开状态，所述开关（1）处于接通状态，并且所述端子（7）被提供有正电位; 其中在所述第三周期之后的第四周期期间，所述终端（7）接地; 并且其中重复第一至第四周期。

89. 发明授权

US06473873B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06473873B1
公开(公告)日：2002-10-29
申请号：US09206534
申请日：1998-12-07
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G06F1100
CPC分类号： G11C29/10 , G11C29/36 , H01L27/10897
摘要： A semiconductor memory device includes: a memory block including a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for use in testing the memory block. A first bus line for coupling the memory block and the test pattern generation circuit has a larger width than that of a second bus line for coupling the memory block to the exterior of the semiconductor memory device.
摘要翻译：半导体存储器件包括：包括多个存储器单元的存储器块; 以及测试图案生成电路，用于生成用于测试存储块的至少一个测试图案。用于耦合存储块和测试图案生成电路的第一总线具有比用于将存储块耦合到半导体存储器件的外部的第二总线的宽度大的宽度。

90. 发明授权

US06400637B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06400637B1
公开(公告)日：2002-06-04
申请号：US09673419
申请日：2000-10-18
申请人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
发明人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/12 , G11C11/4087
摘要： Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.
摘要翻译：提供四个具有分层字线结构的存储体（10至13）。如果通过控制分组（PKT）指定存储器组中的一个的特定模式，则模式识别器（15）产生子字改变使能（SEN0-3）和列更改的前沿使能（CEN-3）信号与主字使能（MEN0-3）信号的逻辑电平固定。这样做是为了使具有相同主字线仍被选择的每个存储体中的子字和列选择线的激活的一个可变。以这种方式，各存储体的行访问速度增加。

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