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1. 发明授权

US07254507B2 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US07254507B2
公开(公告)日：2007-08-07
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R35/02
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

2. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

3. 发明授权

US06466273B1 Analog FIFO memory device 失效
标题翻译：模拟FIFO存储器件
公开(公告)号：US06466273B1
公开(公告)日：2002-10-15
申请号：US09076848
申请日：1998-05-13
申请人： Shiro Dosho , Naoshi Yanagisawa
发明人： Shiro Dosho , Naoshi Yanagisawa
IPC分类号： H04N52136
CPC分类号： G06J1/00
摘要： An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency. That is to say, since a signal band can be separated from the fixed pattern noise in terms of frequency, the fixed pattern noise can be eliminated by a low pass filter. Consequently, even when the analog FIFO memory device of the present invention is applied for delaying TV signals, the resulting TV image quality is not deteriorated.
摘要翻译：模拟FIFO存储器件允许抑制由模拟FIFO存储器内部产生的固定模式噪声对信号分量产生的不利影响。第一和第二模拟乘法器分别设置在模拟FIFO存储器的输入和输出侧。与来自/来自模拟FIFO存储器的信号的输入/输出同步，对输入信号和输出信号交替重复执行非反相操作和反相操作。然后，虽然模拟FIFO存储器的信号输入/输出特性没有改变，但在模拟FIFO存储器内产生的固定模式噪声被第二模拟乘法器调制。结果，原来具有较低频率的固定图案噪声的频谱被移位以具有较高的频率。也就是说，由于信号频带可以根据频率与固定模式噪声分离，因此可以通过低通滤波器消除固定模式噪声。因此，即使当本发明的模拟FIFO存储器件用于延迟TV信号时，所得到的TV图像质量也不会恶化。

4. 发明授权

US06407642B2 Frequency detector and phase-locked loop circuit including the detector 失效
标题翻译：频率检测器和包括检测器的锁相环电路
公开(公告)号：US06407642B2
公开(公告)日：2002-06-18
申请号：US09752525
申请日：2001-01-03
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama
IPC分类号： H03L7085
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.
摘要翻译：包括两个锁存器和一个“与非”门的三态相位检测器具有两个附加锁存器。为了检测第一和第二输入时钟信号R和V之间的相位差，相位检测器响应于输入R或V信号的上升沿在三个状态之间交替。两个附加锁存器中的每一个和相位检测器中的相关锁存器一起构成一个移位寄存器。当相位检测器回到其中性状态时，与非门产生复位信号，从而复位这四个锁存器的全部。还提供了两个隔离的脉冲发生器。每个脉冲发生器使得从相关联的一个附加锁存器输出的频差脉冲信号的脉冲宽度恒定，然后输出具有恒定宽度的脉冲信号。

5. 发明申请

US20090278614A1 PHASE SYNCHRONIZING CIRCUIT 有权
标题翻译：相位同步电路
公开(公告)号：US20090278614A1
公开(公告)日：2009-11-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/08
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

6. 发明授权

US06528982B1 Jitter detector, phase difference detector and jitter detecting method 失效
标题翻译：抖动检测器，相位差检测器和抖动检测方法
公开(公告)号：US06528982B1
公开(公告)日：2003-03-04
申请号：US09697721
申请日：2000-10-27
申请人： Naoshi Yanagisawa , Shiro Dosho , Kazuhiko Nishikawa , Seiji Watanabe , Takahiro Bokui
发明人： Naoshi Yanagisawa , Shiro Dosho , Kazuhiko Nishikawa , Seiji Watanabe , Takahiro Bokui
IPC分类号： G01R2500
CPC分类号： G01R25/00
摘要： A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. The comparison pulse generator outputs one phase difference comparison pulse after another. Each phase difference comparison pulse has a width representing the phase difference between first and second input signals. The periodic signal generator outputs a periodic signal every time a value obtained by accumulating the widths of the phase difference comparison pulses exceeds a predetermined value. Receiving the periodic signal and a clock signal with a period shorter than that of the periodic signal, the counter counts the number of pulses of the clock signal during one period of the periodic signal and outputs a resultant count. And the arithmetic unit detects and outputs a variation in the count as jitter between the first and second input signals.
摘要翻译：抖动检测器获得输入信号之间的相位差作为数字值，使信号之间的抖动容易检测。抖动检测器包括比较脉冲发生器，周期信号发生器，计数器和算术单元。比较脉冲发生器输出一个相差差值比较脉冲。每个相位差比较脉冲具有表示第一和第二输入信号之间的相位差的宽度。每当通过累加相位差比较脉冲的宽度获得的值超过预定值时，周期性信号发生器输出周期信号。接收到周期信号和周期信号的周期信号的时钟信号，计数器在周期信号的一个周期内对时钟信号的脉冲数进行计数，并输出结果计数。并且算术单元检测并输出计数的变化，作为第一和第二输入信号之间的抖动。

7. 发明授权

US06121826A Comb filter and method for controlling the same 失效
标题翻译：梳状滤波器及其控制方法
公开(公告)号：US06121826A
公开(公告)日：2000-09-19
申请号：US210780
申请日：1998-12-15
申请人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
发明人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
IPC分类号： H04N9/78 , H03K5/00
CPC分类号： H04N9/78
摘要： A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal. Accordingly, a large-capacitance capacitor, which has been required for stabilizing the control signal, is no longer necessary.
摘要翻译：提供了一种梳状滤波器，可以在不使用大容量电容器的情况下容易地实现为单片LSI。梳状频率特性由用于延迟相互不同时间量的信号的两个延迟电路和用于导出其输出的和或差的运算电路实现。在图像信号的消隐间隔期间，输入选择开关选择性地输出作为具有预定幅度的DC信号的测试信号而不是图像信号。检测器根据测试信号和预定参考信号之间的梳状滤波器的输出信号之间的差异来控制提供给任一个延迟电路的输出的可变增益放大器的增益。也就是说，通过使用稳定的测试信号作为控制信号来控制梳状滤波器的增益，而不是包含在不稳定图像信号中的突发信号。因此，不再需要用于稳定控制信号所需的大容量电容器。

8. 发明授权

US07978013B2 Phase synchronizing circuit 有权
标题翻译：相位同步电路
公开(公告)号：US07978013B2
公开(公告)日：2011-07-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

9. 发明授权

US06559895B1 Analog memory and image processing system for reducing fixed pattern noise 有权
标题翻译：用于减少固定模式噪声的模拟记忆和图像处理系统
公开(公告)号：US06559895B1
公开(公告)日：2003-05-06
申请号：US09508447
申请日：2000-03-10
申请人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
发明人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
IPC分类号： H04N978
CPC分类号： G11C27/04 , G11C27/024
摘要： Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic. In this manner, charge feed through noise of the respective storage elements (21) are made substantially uniform, resulting in suppressing the fixed pattern noise.
摘要翻译：模拟存储器的固定模式噪声降低。在地址产生单元（10）和用于存储模拟信号的各个存储元件（21）之间的地址选择信号（SL）的传输路径被构造为在通过地址驱动存储元件（21）时具有基本均匀的电特性选择信号（SL）使得模拟存储器的输出信号没有固定模式噪声的程度。用于临时存储和输出地址选择信号的缓冲单元（50）设置在地址生成单元（10）和各个存储元件（21）之间，缓冲单元（50）被构造成具有基本均匀的输出特性在所述存储元件（21）之间。此外，缓冲单元（50）和存储元件（21）之间的线被构造成具有基本上相同的电特性。以这种方式，通过各个存储元件（21）的噪声的电荷馈送被制成基本均匀，导致抑制固定图案噪声。

10. 发明授权

US06982581B2 Duty cycle correction circuit 失效
标题翻译：占空比校正电路
公开(公告)号：US06982581B2
公开(公告)日：2006-01-03
申请号：US10713162
申请日：2003-11-17
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： H03K3/017
CPC分类号： H03K5/133 , H03K5/1565
摘要： In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.
摘要翻译：为了校正给定时钟信号的占空比以产生具有50％占空比的时钟信号，占空比校正电路包括用于延迟第一时钟信号以输出第二时钟信号和时钟信号的延迟单元输出单元。时钟信号输出单元包括使用第一和第二时钟信号作为各个门的输入的两个晶体管，以及用于反相从晶体管的公共漏极输出的信号以输出第三时钟信号的反相器电路。延迟单元延迟第一时钟信号，使得第一时钟信号在占空比变为50％的定时出现。时钟信号输出单元中的两个晶体管响应于第一时钟信号的上升和第二时钟信号的下降而输出作为第三时钟信号的接地电压和源极电压作为来自公共漏极的信号，分别。

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