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    • 1. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06400637B1
    • 2002-06-04
    • US09673419
    • 2000-10-18
    • Hironori AkamatsuToru IwataMakoto Kojima
    • Hironori AkamatsuToru IwataMakoto Kojima
    • G11C800
    • G11C8/14G11C8/12G11C11/4087
    • Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.
    • 提供四个具有分层字线结构的存储体(10至13)。 如果通过控制分组(PKT)指定存储器组中的一个的特定模式,则模式识别器(15)产生子字改变使能(SEN0-3)和列更改的前沿 使能(CEN-3)信号与主字使能(MEN0-3)信号的逻辑电平固定。 这样做是为了使具有相同主字线仍被选择的每个存储体中的子字和列选择线的激活的一个可变。 以这种方式,各存储体的行访问速度增加。
    • 10. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US07123510B2
    • 2006-10-17
    • US11058374
    • 2005-02-16
    • Makoto KojimaTakafumi Maruyama
    • Makoto KojimaTakafumi Maruyama
    • G11C16/04
    • G11C16/04
    • A plurality of memory cells are connected between two adjacent sub-bit lines. A row decoder 3 selects a word line connected to a memory cell to be read. A selection line selection circuit 2 and a column selection circuit 5 include first and second selection portions that perform selection operations simultaneously and independently. The first selection portion selects a first pair of main bit lines and selection lines in order to select the memory cell to be read. The second selection portion selects a second pair of main bit lines that is different from the first pair of main bit lines and selection lines for selecting a sector different from that for the memory cell to be read in order to select a line to be used for reading a reference voltage.
    • 多个存储单元连接在两个相邻的子位线之间。 行解码器3选择连接到要读取的存储单元的字线。 选择线选择电路2和列选择电路5包括同时且独立地执行选择操作的第一和第二选择部分。 第一选择部分选择第一对主位线和选择线,以选择要读取的存储单元。 第二选择部分选择不同于第一对主位线和选择线的第二对主位线,用于选择与要读取的存储单元的扇区不同的扇区,以便选择要用于 读取参考电压。