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1. 发明授权

US07254507B2 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US07254507B2
公开(公告)日：2007-08-07
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R35/02
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

2. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

3. 发明申请

US20050049809A1 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US20050049809A1
公开(公告)日：2005-03-03
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R31/316 , G01R35/00 , G06F19/00
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

4. 发明授权

US06982581B2 Duty cycle correction circuit 失效
标题翻译：占空比校正电路
公开(公告)号：US06982581B2
公开(公告)日：2006-01-03
申请号：US10713162
申请日：2003-11-17
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： H03K3/017
CPC分类号： H03K5/133 , H03K5/1565
摘要： In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.
摘要翻译：为了校正给定时钟信号的占空比以产生具有50％占空比的时钟信号，占空比校正电路包括用于延迟第一时钟信号以输出第二时钟信号和时钟信号的延迟单元输出单元。时钟信号输出单元包括使用第一和第二时钟信号作为各个门的输入的两个晶体管，以及用于反相从晶体管的公共漏极输出的信号以输出第三时钟信号的反相器电路。延迟单元延迟第一时钟信号，使得第一时钟信号在占空比变为50％的定时出现。时钟信号输出单元中的两个晶体管响应于第一时钟信号的上升和第二时钟信号的下降而输出作为第三时钟信号的接地电压和源极电压作为来自公共漏极的信号，分别。

5. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

6. 发明申请

US20060026479A1 Verification vector creating method, and electronic circuit verifying method using the former method 审中-公开
标题翻译：验证矢量创建方法，以及使用前一种方法的电子电路验证方法
公开(公告)号：US20060026479A1
公开(公告)日：2006-02-02
申请号：US11181017
申请日：2005-07-14
申请人： Keijiro Umehara , Masakazu Tanaka
发明人： Keijiro Umehara , Masakazu Tanaka
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G06F11/263 , G01R31/3163
摘要： To realize an equivalence verification between an analog circuit and its function model unit. From a circuit topology and a functional description, there is extracted contained in the circuit. A test circuit capable of inputting a verification vector according to the extracted circuit function is created, and a verification is made to provide a result. In case the equivalence is to be verified, a similar verification is made by replacing only a compared circuit of the test circuit created. After the result was obtained, its difference from the aforementioned result is made. If this difference is within an allowable range, the equivalence is decided. By using the configuration of the invention, the analog circuit or the function model can be verified on itself. Moreover, the equivalence can be verified with the minimum configuration.
摘要翻译：实现模拟电路与其功能模型单元之间的等效性验证。从电路拓扑和功能描述中，提取包含在电路中。创建能够根据提取的电路功能输入验证矢量的测试电路，并且进行验证以提供结果。在等待验证的情况下，通过仅替换所创建的测试电路的比较电路进行类似的验证。得到结果后，与上述结果不同。如果该差异在允许范围内，则确定等价物。通过使用本发明的结构，可以自己验证模拟电路或功能模型。此外，可以用最小配置验证等价性。

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