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1. 发明授权

US06809953B2 Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof 有权
标题翻译：电位发生电路，电位产生装置及使用其的半导体装置及其驱动方法
公开(公告)号：US06809953B2
公开(公告)日：2004-10-26
申请号：US10440277
申请日：2003-05-16
申请人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
发明人： Kenji Toyoda , Michihito Ueda , Kiyoshi Morimoto , Kiyoyuki Morita , Toru Iwata , Jun Kajiwara
IPC分类号： G11C1122
CPC分类号： H02M3/07 , H02M3/073
摘要： A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through fourth periods are repeated.
摘要翻译：电位发生电路包括电容器（4）; 与电容器（4）串联连接的铁电电容器（6）。输出端子（11）; 用于使输出端子（11）接地的电容器（10）; 用于将两个电容器（4,6）之间的连接节点（5）连接到输出端子（11）的开关（9）; 和用于将连接节点（5）连接到地面的开关（1）; 其中在第一时段期间，当开关（1）和（9）处于断开状态时，端子（3）被提供有正电位并且端子（7）接地; 其中在所述第一周期之后的第二时段期间，所述端子（3）接地，并且所述开关（9）处于接通状态; 其中在所述第二时段之后的第三时段期间，所述开关（9）处于断开状态，所述开关（1）处于接通状态，并且所述端子（7）被提供有正电位; 其中在所述第三周期之后的第四周期期间，所述终端（7）接地; 并且其中重复第一至第四周期。

2. 发明授权

US09046110B2 Crossflow fan and air conditioner provided with same 有权
标题翻译：交叉风扇和空调配备相同
公开(公告)号：US09046110B2
公开(公告)日：2015-06-02
申请号：US13255196
申请日：2010-03-09
申请人： Hironobu Teraoka , Shimei Tei , Toru Iwata
发明人： Hironobu Teraoka , Shimei Tei , Toru Iwata
IPC分类号： F01D5/14 , F04D29/28 , F04D17/04 , F04D29/30 , F24F1/00
CPC分类号： F04D29/283 , F04D17/04 , F04D29/30 , F04D29/681 , F24F1/0025 , F24F2001/0048
摘要： A crossflow fan includes a rotary impeller formed by curved blades 42. Each of the blades 42 has an outer peripheral edge 43 close to the centrifugal side of the impeller and an inner peripheral edge 44 close to the rotation axis side of the impeller. A plurality of cutouts 45 are formed in the outer peripheral edge 43 and spaced apart at predetermined intervals. Dimples 48 for changing a boundary layer from a laminar flow to a turbulent flow are formed in a negative pressure surface 4q of each blade 42 in the vicinity of the outer peripheral edge 43 to prevent the gas flowing around the blade 42 from separating from the blade 42.
摘要翻译：横流风扇包括由弯曲叶片42形成的旋转叶轮。每个叶片42具有靠近叶轮的离心侧的外周边缘43和靠近叶轮的旋转轴线侧的内周边缘44。多个切口45形成在外周边缘43中并且以预定间隔隔开。在每个叶片42的外周边缘43附近的负压表面4q中形成用于将边界层从层流改变为湍流的凹坑48，以防止在叶片42周围流动的气体与叶片分离 42。

3. 发明申请

US20120003579A1 FERRITE CARRIER CORE MATERIAL AND FERRITE CARRIER FOR ELECTROPHOTOGRAPHIC DEVELOPER, AND ELECTROPHOTOGRAPHIC DEVELOPER USING THE FERRITE CARRIER 有权
标题翻译：电子雕刻机的铁素体核心材料和铁素体载体，以及使用铁素体载体的电子显影开发
公开(公告)号：US20120003579A1
公开(公告)日：2012-01-05
申请号：US13161697
申请日：2011-06-16
申请人： Toru Iwata , Koji Aga
发明人： Toru Iwata , Koji Aga
IPC分类号： G03G9/107 , G03G9/113
CPC分类号： G03G9/107 , G03G9/1075 , G03G9/1133 , G03G9/1139
摘要： There are provided a ferrite carrier core material for an electrophotographic developer, which contain 10 to 30% by weight of Mn, 1.0 to 3.0% by weight of Mg, 0.3 to 1.5% by weight of Ti and 40 to 60% by weight of Fe, a ferrite carrier for an electrophotographic developer obtained by coating the ferrite core material, and an electrophotographic developer using the ferrite carrier.
摘要翻译：提供了一种用于电子照相显影剂的铁氧体载体芯材，其含有10至30重量％的Mn，1.0至3.0重量％的Mg，0.3至1.5重量％的Ti和40至60重量％的Fe ，通过涂布铁氧体芯材获得的用于电子照相显影剂的铁氧体载体和使用该铁氧体载体的电子照相显影剂。

4. 发明申请

US20100245663A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND TRANSMITTER APPARATUS HAVING THE SAME 有权
标题翻译：半导体集成电路及其发送装置
公开(公告)号：US20100245663A1
公开(公告)日：2010-09-30
申请号：US12376405
申请日：2007-07-31
申请人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
发明人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
IPC分类号： H04N7/01 , G06F1/04 , H04N5/05
CPC分类号： H03K5/135 , H03L7/18 , H03M9/00 , H04L7/0008
摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
摘要翻译：一种用于接收并行数据信号和第一时钟信号并输出串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟信号X / Y。第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号缩放器（16），与第四时钟信号同步地连接到串行数据信号。分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟信号之一作为第二时钟信号。

5. 发明授权

US07782103B2 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US07782103B2
公开(公告)日：2010-08-24
申请号：US11513023
申请日：2006-08-31
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H03L7/0812 , H04L7/0037 , H04L7/0337
摘要： A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
摘要翻译：一种相位调整电路，用于离散地调整数据信号的相位和时钟信号的相位，所述相位调整电路包括：延迟线，用于延迟所述时钟信号以产生延迟的时钟信号; 相位比较器，用于比较数据信号的相位与延迟的时钟信号的相位; 延迟控制部分，用于基于来自相位比较器的比较结果输出延迟控制信号; 以及延迟控制部分，用于基于时钟信号的频率输出延迟控制信号。延迟线基于控制信号确定相对于时钟信号的延迟时钟信号的延迟量。

6. 发明授权

US07480548B2 High-altitude capable wide velocity range flight velocity vector measurement probe and measurement system 有权
标题翻译：高空能力宽速度范围飞行速度矢量测量探头和测量系统
公开(公告)号：US07480548B2
公开(公告)日：2009-01-20
申请号：US11224030
申请日：2005-09-13
申请人： Masashi Shigemi , Akira Koike , Makoto Ueno , Tomonari Hirotani , Teruomi Nakaya , Hiroshi Wakai , Toru Iwata
发明人： Masashi Shigemi , Akira Koike , Makoto Ueno , Tomonari Hirotani , Teruomi Nakaya , Hiroshi Wakai , Toru Iwata
IPC分类号： G01P5/165 , G01P5/175
CPC分类号： G01P5/175 , G01C5/005 , G01P5/16 , G01P13/025
摘要： It is an object of the present invention to solve the problem of a drop in precision in conventional systems using a square pyramid type five-hole probe due to the drop in atmospheric pressure in high altitude ranges, and to provide a wide velocity range flight velocity vector measurement system that can prevent a drop in measurement precision. Furthermore, it is also an object of the present invention to provide a method for eliminating the effects of detection fluctuations caused by adhering water droplets, ice particles or dust in a wide velocity range flight velocity vector measurement system. The flight velocity vector measurement probe of the present invention comprises means in which a static pressure hole is formed in the tube wall surface of the probe, so that a static pressure value is obtained from the pressure detected by this static pressure hole, the Mach number M is calculated on the basis of an equation approximated by a fourth-order polynomial of the static pressure/total pressure signal and the angle of attack, and in cases where an abnormal detection value is detected, this is replaced by the preceding detection value.
摘要翻译：本发明的一个目的是解决由于在高海拔范围内的大气压力下降而使用方形棱锥型五孔探针的常规系统的精度下降的问题，并且提供宽的速度范围飞行速度矢量测量系统，可以防止测量精度下降。此外，本发明的另一个目的是提供一种消除在宽速度范围飞行速度矢量测量系统中粘附水滴，冰粒或灰尘引起的检测波动的影响的方法。本发明的飞行速度矢量测量探头包括在探针的管壁表面中形成静压孔的装置，从而由该静压孔检测到的压力获得静压值，马赫数基于由静压/总压力信号的四次多项式近似的方程式计算出M，并且在检测到异常检测值的情况下，将其替换为前一检测值。

7. 发明授权

US07204096B2 Indoor apparatus for air conditioner 有权
标题翻译：空调室内机
公开(公告)号：US07204096B2
公开(公告)日：2007-04-17
申请号：US10533200
申请日：2003-10-30
申请人： Toru Iwata , Masakazu Hirai
发明人： Toru Iwata , Masakazu Hirai
IPC分类号： F25D17/06
CPC分类号： F24F1/0007 , F24F1/0011 , F24F1/0022 , F24F2001/0037
摘要： An air discharge outlet comprises line air discharge outlets (35) and corner air discharge outlets (36). The line air discharge outlets (35) are so formed as to extend, respectively, along four sides of a casing bottom part having four side parts and four corner parts wherein the side and corner parts are formed in contiguous relationship to one another. The corner air discharge outlets (36) are formed, respectively, in the four casing corner parts so that each corner air discharge outlet (36) establishes connection between adjacent ones of the line air discharge outlets (35). And, each line air discharge outlet (35) is provided with a swing vane (38) swingable about a longitudinal shaft (41) of each line air discharge outlet (35). Each corner air discharge outlet (36) is provided with a fixed stationary vane (39).
摘要翻译：空气排出口包括排气出口（35）和角空气排出口（36）。线排出口35形成为分别沿着具有四个侧面部分和四个拐角部分的壳体底部的四个侧面延伸，其中侧部和拐角部分彼此连续地形成。角空气排出口36分别形成在四个壳体角部，使得每个角空气排出口36建立相邻的排气出口35之间的连接。并且，每排排气口（35）设置有可围绕每排排气口（35）的纵轴（41）摆动的摆动叶片（38）。每个角空气排出口（36）设置有固定静止叶片（39）。

8. 发明申请

US20070080728A1 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US20070080728A1
公开(公告)日：2007-04-12
申请号：US11513023
申请日：2006-08-31
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H03L7/0812 , H04L7/0037 , H04L7/0337
摘要： A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
摘要翻译：一种相位调整电路，用于离散地调整数据信号的相位和时钟信号的相位，所述相位调整电路包括：延迟线，用于延迟所述时钟信号以产生延迟的时钟信号; 相位比较器，用于比较数据信号的相位与延迟的时钟信号的相位; 延迟控制部分，用于基于来自相位比较器的比较结果输出延迟控制信号; 以及延迟控制部分，用于基于时钟信号的频率输出延迟控制信号。延迟线基于控制信号确定相对于时钟信号的延迟时钟信号的延迟量。

9. 发明申请

US20050069032A1 Analog equalizer 审中-公开
标题翻译：模拟均衡器
公开(公告)号：US20050069032A1
公开(公告)日：2005-03-31
申请号：US10947382
申请日：2004-09-23
申请人： Takashi Hirata , Toru Iwata , Noriaki Takeda
发明人： Takashi Hirata , Toru Iwata , Noriaki Takeda
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159 , H03L7/06 , H03L7/081 , H04B1/12 , H04B3/04 , H04B7/005 , H04L25/03
CPC分类号： H03L7/06 , H03K5/133 , H03K2005/00026 , H03L7/0805 , H03L7/0812 , H04L25/03885
摘要： An analog equalizer includes a mixer and an analog delay circuit. The mixer mixes an input signal and a delayed signal output from the analog delay circuit to output a mixed signal. The analog delay circuit delays the mixed signal output from the mixer to output a delayed signal.
摘要翻译：模拟均衡器包括混频器和模拟延迟电路。混合器混合输入信号和从模拟延迟电路输出的延迟信号以输出混合信号。模拟延迟电路延迟从混频器输出的混合信号以输出延迟信号。

10. 发明授权

US06393577B1 Semiconductor integrated circuit system, semiconductor integrated circuit and method for driving semiconductor integrated circuit system 失效
标题翻译：半导体集成电路系统，半导体集成电路及半导体集成电路系统驱动方法
公开(公告)号：US06393577B1
公开(公告)日：2002-05-21
申请号：US09115716
申请日：1998-07-15
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G06F1342
CPC分类号： G06F1/025 , G06F1/10 , H03L7/06
摘要： The present invention provides a semiconductor integrated circuit system, having one master chip and a plurality of slave chips, for performing data transfer under a control of a predetermined clock. The system includes: a detection section for detecting a change in a state of the semiconductor integrated circuit system and for producing information indicating the detection result, the state including at least one of temperature and source voltage; and at least one clock phase adjustment section for receiving the information and for adjusting a phase of a clock used in transferring data output by the slave chip based on the information.
摘要翻译：本发明提供一种具有一个主芯片和多个从芯片的半导体集成电路系统，用于在预定时钟的控制下执行数据传输。该系统包括：检测部分，用于检测半导体集成电路系统的状态变化，并产生指示检测结果的信息，该状态包括温度和电源电压中的至少一个; 以及至少一个时钟相位调整部分，用于接收所述信息并且用于根据所述信息调整用于传送由所述从芯片输出的数据所使用的时钟的相位。

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