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1. 发明授权

US06400637B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06400637B1
公开(公告)日：2002-06-04
申请号：US09673419
申请日：2000-10-18
申请人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
发明人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/12 , G11C11/4087
摘要： Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.
摘要翻译：提供四个具有分层字线结构的存储体（10至13）。如果通过控制分组（PKT）指定存储器组中的一个的特定模式，则模式识别器（15）产生子字改变使能（SEN0-3）和列更改的前沿使能（CEN-3）信号与主字使能（MEN0-3）信号的逻辑电平固定。这样做是为了使具有相同主字线仍被选择的每个存储体中的子字和列选择线的激活的一个可变。以这种方式，各存储体的行访问速度增加。

2. 发明授权

US06393577B1 Semiconductor integrated circuit system, semiconductor integrated circuit and method for driving semiconductor integrated circuit system 失效
标题翻译：半导体集成电路系统，半导体集成电路及半导体集成电路系统驱动方法
公开(公告)号：US06393577B1
公开(公告)日：2002-05-21
申请号：US09115716
申请日：1998-07-15
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G06F1342
CPC分类号： G06F1/025 , G06F1/10 , H03L7/06
摘要： The present invention provides a semiconductor integrated circuit system, having one master chip and a plurality of slave chips, for performing data transfer under a control of a predetermined clock. The system includes: a detection section for detecting a change in a state of the semiconductor integrated circuit system and for producing information indicating the detection result, the state including at least one of temperature and source voltage; and at least one clock phase adjustment section for receiving the information and for adjusting a phase of a clock used in transferring data output by the slave chip based on the information.
摘要翻译：本发明提供一种具有一个主芯片和多个从芯片的半导体集成电路系统，用于在预定时钟的控制下执行数据传输。该系统包括：检测部分，用于检测半导体集成电路系统的状态变化，并产生指示检测结果的信息，该状态包括温度和电源电压中的至少一个; 以及至少一个时钟相位调整部分，用于接收所述信息并且用于根据所述信息调整用于传送由所述从芯片输出的数据所使用的时钟的相位。

3. 发明授权

US5734604A Static random access memory capable of both reducing power consumption and retaining data at standby-time 失效
标题翻译：静态随机存取存储器能够在待机时减少功耗并保留数据
公开(公告)号：US5734604A
公开(公告)日：1998-03-31
申请号：US739392
申请日：1996-10-29
申请人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
发明人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
IPC分类号： G11C11/412 , G11C11/417 , G11C11/413
CPC分类号： G11C11/412 , G11C11/417
摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.
摘要翻译：当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。结果，接地电源线的电压从电源VSS的电压增加。因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

4. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

5. 发明授权

US5999022A Signal transmission driver circuit, receiver circuit, and method thereof for transmitting and receiving information based on multiple periods and/or a delay function 失效
标题翻译：用于基于多个周期和/或延迟功能发送和接收信息的信号传输驱动电路，接收机电路及其方法
公开(公告)号：US5999022A
公开(公告)日：1999-12-07
申请号：US631914
申请日：1996-04-15
申请人： Toru Iwata , Hironori Akamatsu , Hisakazu Kotani , Hiroyuki Yamauchi , Akira Matsuzawa , Shoichiro Tada
发明人： Toru Iwata , Hironori Akamatsu , Hisakazu Kotani , Hiroyuki Yamauchi , Akira Matsuzawa , Shoichiro Tada
IPC分类号： H03K19/00 , H03K19/0185 , H03K3/00
CPC分类号： H03K19/01855 , H03K19/0016
摘要： A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.
摘要翻译：驱动信号线的驱动器电路包括：第一输出部，用于在第一时段期间向信号线输出参考电压电位;以及第二输出部，用于输出第一信息电压电位和第二信息电压电位之一在第二时段期间的输入信号。

6. 发明授权

US5757702A Data holding circuit 失效
标题翻译：数据保持电路
公开(公告)号：US5757702A
公开(公告)日：1998-05-26
申请号：US739363
申请日：1996-10-29
申请人： Toru Iwata , Hironori Akamatsu , Hiroyuki Yamauchi
发明人： Toru Iwata , Hironori Akamatsu , Hiroyuki Yamauchi
IPC分类号： G11C11/412 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.
摘要翻译：存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于施加到外围电路的接地电压。

7. 发明授权

US06944003B2 Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
标题翻译：具有电压检测电路和信号发射和接收系统的半导体集成电路
公开(公告)号：US06944003B2
公开(公告)日：2005-09-13
申请号：US10365527
申请日：2003-02-13
申请人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
发明人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
IPC分类号： G01R31/28 , H01L21/66 , H02H9/04 , H02H3/24
CPC分类号： H02H9/046
摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.
摘要翻译：第一半导体集成电路通过电缆连接到第二半导体集成电路。在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作强制。因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。因此，在低电压条件下可以进行运行评估。

8. 发明授权

US06201412B1 Semiconductor integrated circuit with driver stabilization using parasitic capacitance 失效
标题翻译：具有驱动器稳定的半导体集成电路使用寄生电容
公开(公告)号：US06201412B1
公开(公告)日：2001-03-13
申请号：US09123902
申请日：1998-07-28
申请人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
发明人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01707
摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.
摘要翻译：本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

9. 发明授权

US5764566A Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
标题翻译：静态随机存取存储器能够降低待机功耗和漏电流
公开(公告)号：US5764566A
公开(公告)日：1998-06-09
申请号：US893682
申请日：1997-07-11
申请人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
发明人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
IPC分类号： G11C11/412 , G11C11/417 , G11C11/413
CPC分类号： G11C11/412 , G11C11/417
摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.
摘要翻译：当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。结果，接地电源线的电压从电源VSS的电压增加。因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

10. 发明授权

US06633607B1 Semiconductor device having a plurality of semiconductor chips connected together by a bus 有权
标题翻译：具有通过总线连接在一起的多个半导体芯片的半导体装置
公开(公告)号：US06633607B1
公开(公告)日：2003-10-14
申请号：US09249695
申请日：1999-02-12
申请人： Hironori Akamatsu , Toru Iwata , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Toru Iwata , Hiroyuki Yamauchi
IPC分类号： H03K904
CPC分类号： H03M9/00 , H04L25/49
摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.
摘要翻译：一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码用于解码位位置信息以产生数据。

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