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81. 发明授权

US08637365B2 Spacer isolation in deep trench 有权
公开(公告)号：US08637365B2
公开(公告)日：2014-01-28
申请号：US13489572
申请日：2012-06-06
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L29/0649 , H01L27/10829 , H01L27/10861 , H01L27/10867 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

82. 发明授权

US08564069B1 Field effect transistors with low body resistance and self-balanced body potential 有权
标题翻译：具有低体电阻和自平衡体电位的场效应晶体管
公开(公告)号：US08564069B1
公开(公告)日：2013-10-22
申请号：US13590212
申请日：2012-08-21
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L27/027 , H01L29/0615 , H01L29/78
摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.
摘要翻译：本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构，邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上垂直于有源栅极的宽度。

83. 发明授权

US08473621B2 Method, system, and apparatus for creating content-on-demand service 有权
标题翻译：用于创建内容点播服务的方法，系统和设备
公开(公告)号：US08473621B2
公开(公告)日：2013-06-25
申请号：US12892608
申请日：2010-09-28
申请人： Jincheng Li , Dongming Zhu , Jianfeng Zhong , Geng Wang , Xiao Wang , Shumin Cheng
发明人： Jincheng Li , Dongming Zhu , Jianfeng Zhong , Geng Wang , Xiao Wang , Shumin Cheng
IPC分类号： G06F15/16
CPC分类号： H04L65/1033 , H04L65/1016 , H04L65/1069 , H04L65/4084 , H04L65/608
摘要： A method, a system, and an apparatus for creating a Content-on-Demand (CoD) service are disclosed herein. The method includes receiving a Session Initiation Protocol (SIP) service request sent by a User Equipment (UE); converting the SIP service request into a Real-Time Streaming Protocol (RTSP) service request, and sending the RTSP service request to a server; receiving an RTSP service response sent by the server; and converting the RTSP service response into a SIP service response, and sending the SIP service response to the UE to create the CoD service between the UE and the server.
摘要翻译：本文公开了一种用于创建内容点播（CoD）服务的方法，系统和装置。该方法包括接收由用户设备（UE）发送的会话发起协议（SIP）服务请求; 将SIP服务请求转换为实时流协议（RTSP）服务请求，并将RTSP服务请求发送到服务器; 接收由服务器发送的RTSP服务响应; 并将RTSP服务响应转换成SIP服务响应，并向UE发送SIP服务响应以在UE与服务器之间创建CoD服务。

84. 发明申请

US20130105898A1 Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices 有权
标题翻译：嵌入式半导体绝缘体器件的单晶硅和漏极
公开(公告)号：US20130105898A1
公开(公告)日：2013-05-02
申请号：US13285162
申请日：2011-10-31
申请人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
发明人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/84 , H01L27/1203
摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.
摘要翻译：在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部，衬底，从而形成源极沟槽和漏极沟槽。在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于顶部半导体层的厚度。

85. 发明授权

US08421139B2 Structure and method to integrate embedded DRAM with finfet 有权
标题翻译：嵌入式DRAM与finfet的结构和方法
公开(公告)号：US08421139B2
公开(公告)日：2013-04-16
申请号：US12755487
申请日：2010-04-07
申请人： Sivananda Kanakasabapathy , Hemanth Jagannathan , Geng Wang
发明人： Sivananda Kanakasabapathy , Hemanth Jagannathan , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/10826 , H01L21/26586 , H01L21/845 , H01L27/10879 , H01L27/10891 , H01L27/1211
摘要： A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.
摘要翻译：晶体管包括第一鳍结构和形成在衬底上的至少第二鳍结构。在第一和第二翅片结构之间形成深沟槽区域。深沟槽区域延伸穿过衬底的绝缘体层和衬底的半导体层。在深沟槽区域内形成高k金属栅极。在与金属层相邻的深沟槽区域内形成多晶硅层。多晶硅层和高k金属层凹陷在绝缘体层的顶表面下方。深沟槽区域中的多晶带形成在高k金属栅极和多晶硅材料的顶部上。该多晶带的尺寸被设计成在第一和第二鳍结构的顶表面下方。第一翅片结构和第二翅片结构电耦合到多晶带。

86. 发明申请

US20130032859A1 EPITAXIAL EXTENSION CMOS TRANSISTOR 有权
标题翻译：外延扩展CMOS晶体管
公开(公告)号：US20130032859A1
公开(公告)日：2013-02-07
申请号：US13198152
申请日：2011-08-04
申请人： Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
摘要翻译：通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一并且通过形成大于第一深度的第二深度的一对第二沟槽。去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

87. 发明申请

US20120286392A1 SUPPRESSION OF DIFFUSION IN EPITAXIAL BURIED PLATE FOR DEEP TRENCHES 失效
标题翻译：抑制深海IN IN。ED。。。。。。。。。。。。。。。
公开(公告)号：US20120286392A1
公开(公告)日：2012-11-15
申请号：US13106349
申请日：2011-05-12
申请人： Chengwen Pei , Geng Wang
发明人： Chengwen Pei , Geng Wang
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L29/66181 , H01L21/2652 , H01L27/10829 , H01L27/10861 , H01L27/10897 , H01L29/945
摘要： Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.
摘要翻译：将第一导电类型的掺杂剂注入到具有第一导电类型的掺杂的半导体衬底的顶部中，以增加作为第一导电型半导体层的顶部中的掺杂剂浓度。在其上形成具有第二导电类型的掺杂的半导体材料层，掩埋绝缘体层和顶部半导体层。具有窄宽度的深沟槽具有在第二导电型半导体层内的底表面，其用作掩埋板。具有较宽宽度的深沟槽被蚀刻到下面的第一导电类型层中，并且可用于形成隔离结构。第一导电型半导体层中的附加掺杂剂提供反向掺杂以抵抗第二导电类型的掺杂剂的向下扩散以增强电隔离。

88. 发明授权

US08299530B2 Structure and method to fabricate pFETS with superior GIDL by localizing workfunction 失效
标题翻译：通过定位功能来制造具有优异GIDL的pFETS的结构和方法
公开(公告)号：US08299530B2
公开(公告)日：2012-10-30
申请号：US12717375
申请日：2010-03-04
申请人： Chengwen Pei , Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L21/22 , H01L21/8238 , H01L27/092
摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.
摘要翻译：提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为适应平带，但不影响设备通道区域的功能。该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。通过离子注入或退火可形成局部功能调谐区域。

89. 发明授权

US08298908B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08298908B2
公开(公告)日：2012-10-30
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

90. 发明申请

US20120205732A1 INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT 有权
标题翻译：集成电路，包含通过过度接触电路连接到TRENCH电容器的有源晶体管
公开(公告)号：US20120205732A1
公开(公告)日：2012-08-16
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, JR. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, JR. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

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