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1. 发明申请

US20130009277A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20130009277A1
公开(公告)日：2013-01-10
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/06
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

2. 发明授权

US08298908B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08298908B2
公开(公告)日：2012-10-30
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

3. 发明申请

US20110193193A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20110193193A1
公开(公告)日：2011-08-11
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

4. 发明授权

US08637958B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

5. 发明申请

US20130295740A1 FORMING CMOS WITH CLOSE PROXIMITY STRESSORS 有权
标题翻译：形成具有紧密接近压力的CMOS
公开(公告)号：US20130295740A1
公开(公告)日：2013-11-07
申请号：US13465159
申请日：2012-05-07
申请人： Desmond J. Donegan, JR. , Abhishek Dube , Steven Jones , JOPHY S. KOSHY , Viorel Ontalus
发明人： Desmond J. Donegan, JR. , Abhishek Dube , Steven Jones , JOPHY S. KOSHY , Viorel Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/66628 , H01L29/66636
摘要： A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.
摘要翻译：提供了一种形成具有接近应力的晶体管到晶体管的沟道区域的方法。该方法包括在衬底的第一区域中形成第一晶体管，在衬底的第一区域的顶部上具有栅极叠层，以及邻近栅堆叠的侧壁的一组间隔物，第一区域包括源极和漏极第一晶体管的区域; 在所述衬底的第二区域中形成第二晶体管，在所述衬底的所述第二区域的顶部上具有栅极叠层，以及邻近所述栅极叠层的侧壁的一组间隔区，所述第二区域包括所述栅极叠层的源极和漏极区域第二晶体管; 用光致抗蚀剂掩模覆盖第一晶体管而不覆盖第二晶体管; 在所述第二晶体管的源极和漏极区域中产生凹陷; 并在凹槽中形成应力源。

6. 发明授权

US08492234B2 Field effect transistor device 有权
公开(公告)号：US08492234B2
公开(公告)日：2013-07-23
申请号：US12825791
申请日：2010-06-29
申请人： Kevin K. Chan , Abhishek Dube , Eric C. Harley , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman , Linda R. Black
发明人： Kevin K. Chan , Abhishek Dube , Eric C. Harley , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman , Linda R. Black
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L21/823412 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78618 , H01L29/78684
摘要： A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

7. 发明授权

US08389352B2 Silicon germanium film formation method and structure 有权
标题翻译：硅锗成膜方法及结构
公开(公告)号：US08389352B2
公开(公告)日：2013-03-05
申请号：US13025474
申请日：2011-02-11
申请人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
发明人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/76224 , H01L21/823807
摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.
摘要翻译：在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。导致沉积的SiGe基本上没有生长边缘效应。

8. 发明授权

US08361859B2 Stressed transistor with improved metastability 有权
标题翻译：具有改善的亚稳态的强调晶体管
公开(公告)号：US08361859B2
公开(公告)日：2013-01-29
申请号：US12942289
申请日：2010-11-09
申请人： Thomas N. Adam , Stephen W. Bedell , Abhishek Dube , Eric C. T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
发明人： Thomas N. Adam , Stephen W. Bedell , Abhishek Dube , Eric C. T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76805 , H01L21/76877 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
摘要翻译：在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

9. 发明授权

US08354314B2 Silicon germanium film formation method and structure 有权
公开(公告)号：US08354314B2
公开(公告)日：2013-01-15
申请号：US13025474
申请日：2011-02-11
申请人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
发明人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
IPC分类号： H01L21/8238
摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

10. 发明授权

US08084788B2 Method of forming source and drain of a field-effect-transistor and structure thereof 有权
标题翻译：形成场效应晶体管的源极和漏极的方法及其结构
公开(公告)号：US08084788B2
公开(公告)日：2011-12-27
申请号：US12248970
申请日：2008-10-10
申请人： Judson Robert Holt , Abhishek Dube , Eric C. T. Harley , Shwu-Jen Jeng , Jeremy J Kempisty , Hasan Munir Nayfeh , Keith Howard Tabakman
发明人： Judson Robert Holt , Abhishek Dube , Eric C. T. Harley , Shwu-Jen Jeng , Jeremy J Kempisty , Hasan Munir Nayfeh , Keith Howard Tabakman
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L29/7848 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.
摘要翻译：公开了涉及使用eSiGe的半导体制造方法。 eSiGe方法对于将期望的应力施加到场效应晶体管的沟道区域是有用的，但是也可能在半导体制造工艺中引入复杂性。本发明的实施方案公开了两步制备方法，其中使用低氢气流速施加第一层eSiGe，并且使用更高的氢气流速施加第二eSiGe层。这种方法提供了一种平衡形态权衡的方法，并在使用eSiGe时填补一致性。本发明的实施例促进了钉扎形态，其降低了对外延厚度的器件灵敏度，同时还在各种器件宽度之间提供更一致的填充体积，从而提供更一致的eSiGe半导体制造工艺。

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