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1. 发明授权

US08691697B2 Self-aligned devices and methods of manufacture 失效
标题翻译：自对准装置和制造方法
公开(公告)号：US08691697B2
公开(公告)日：2014-04-08
申请号：US12943956
申请日：2010-11-11
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31056 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
摘要翻译：一种方法包括在具有预定间距的基底上形成图案线。该方法还包括在图案化线的侧壁上形成间隔壁。该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。该方法还包括将图案化线和另一图案化线的图案转移到衬底。

2. 发明授权

US08575670B2 Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate 有权
标题翻译：在非常薄的半导体绝缘体（ETSOI）衬底上形成的嵌入式动态随机存取存储器件
公开(公告)号：US08575670B2
公开(公告)日：2013-11-05
申请号：US13316056
申请日：2011-12-09
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10861 , H01L28/91 , H01L29/945
摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
摘要翻译：一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。电容器存在于沟槽的下部。电介质垫片存在于沟槽上部的侧壁上。介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。导电材料填充物存在于沟槽的上部。半导体器件存在于与沟槽相邻的SOI层上。半导体器件通过导电材料填充与电容器电连通。

3. 发明授权

US08809994B2 Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate 有权
标题翻译：绝缘体上半导体衬底上的深度隔离沟槽结构和深沟槽电容器
公开(公告)号：US08809994B2
公开(公告)日：2014-08-19
申请号：US13316104
申请日：2011-12-09
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/70
CPC分类号： H01L27/1087 , H01L27/10829 , H01L27/1203 , H01L29/945
摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
摘要翻译：在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。在沟槽中形成不透氧层和填充材料层。从第一沟槽内去除填充材料层和不透氧层。执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

4. 发明申请

US20140070292A1 DEEP TRENCH CAPACITOR 有权
标题翻译：深层电容电容
公开(公告)号：US20140070292A1
公开(公告)日：2014-03-13
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L21/311
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译：提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂散装衬底形成掩埋板。该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部，去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

5. 发明申请

US20130328157A1 SPACER ISOLATION IN DEEP TRENCH 有权
标题翻译：深层隔离器中的间隔隔离
公开(公告)号：US20130328157A1
公开(公告)日：2013-12-12
申请号：US13489572
申请日：2012-06-06
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0649 , H01L27/10829 , H01L27/10861 , H01L27/10867 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.
摘要翻译：在深沟槽中形成改进的间隔隔离的方法，包括将形成在绝缘体上硅（SOI）衬底中的深沟槽内沉积的节点电介质，第一导电层和第二导电层凹入到低于 SOI衬底的掩埋氧化物层，并且在深沟槽中形成具有底表面的开口。还包括沿深沟槽的侧壁和开口的底表面沉积间隔物，以及从开口的底表面移除隔离物。在一个方向上以一定角度进行离子注入和离子轰击中的至少一个进入间隔物的上部。从深沟槽的侧壁上去除隔离物的上部。在开口内沉积第三导电层。

6. 发明授权

US08409989B2 Structure and method to fabricate a body contact 有权
标题翻译：制造身体接触的结构和方法
公开(公告)号：US08409989B2
公开(公告)日：2013-04-02
申请号：US12944174
申请日：2010-11-11
申请人： Chengwen Pei , Roger Allen Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger Allen Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/72
CPC分类号： H01L29/49 , H01L21/743 , H01L21/823475 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.
摘要翻译：公开了一种在晶体管上制造体接触的结构和方法。该方法包括在处理晶片上形成具有晶体管的半导体结构。然后将结构反转，并移除手柄晶片。然后在倒置位置的晶体管上形成硅化物体接触。身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

7. 发明申请

US20120306049A1 METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE 有权
标题翻译：金属电镀电容器和改进的隔离和制造方法
公开(公告)号：US20120306049A1
公开(公告)日：2012-12-06
申请号：US13153538
申请日：2011-06-06
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/743 , H01L21/76283 , H01L27/0629 , H01L27/108 , H01L27/1087 , H01L27/1203 , H01L28/60 , H01L28/92 , H01L29/0649 , H01L29/66181
摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
摘要翻译：提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

8. 发明申请

US20120305998A1 HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY 有权
标题翻译：高密度记忆细胞使用横向外延
公开(公告)号：US20120305998A1
公开(公告)日：2012-12-06
申请号：US13118881
申请日：2011-05-31
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L29/92 , H01L27/10829 , H01L27/10861 , H01L27/1203
摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.
摘要翻译：在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

9. 发明申请

US20110215412A1 STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION 失效
标题翻译：通过局部化工作来形成具有超级GIDL的结构和方法
公开(公告)号：US20110215412A1
公开(公告)日：2011-09-08
申请号：US12717375
申请日：2010-03-04
申请人： Chengwen Pei , Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L21/22
CPC分类号： H01L21/22 , H01L21/8238 , H01L27/092
摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.
摘要翻译：提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为适应平带，但不影响设备通道区域的功能。该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。通过离子注入或退火可形成局部功能调谐区域。

10. 发明授权

US09048339B2 Deep trench capacitor 有权
标题翻译：深沟槽电容器
公开(公告)号：US09048339B2
公开(公告)日：2015-06-02
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L27/108 , H01L27/12
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译：提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂散装衬底形成掩埋板。该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部，去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

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