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71. 发明授权

US06563759B2 Semiconductor memory device 有权
公开(公告)号：US06563759B2
公开(公告)日：2003-05-13
申请号：US09871911
申请日：2001-06-04
申请人： Hideharu Yahata , Masashi Horiguchi , Hiroki Fujisawa , Tsugio Takahashi , Masayuki Nakamura
发明人： Hideharu Yahata , Masashi Horiguchi , Hiroki Fujisawa , Tsugio Takahashi , Masayuki Nakamura
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4082 , G11C11/4087
摘要： In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).

72. 发明授权

US06563750B2 Semiconductor memory including a circuit for selecting redundant memory cells 有权
标题翻译：半导体存储器，包括用于选择冗余存储单元的电路
公开(公告)号：US06563750B2
公开(公告)日：2003-05-13
申请号：US10134521
申请日：2002-04-30
申请人： Hiroshi Otori , Hiroki Fujisawa , Minoru Ebihara , Seiji Narui , Masanori Isoda , Akira Ohta
发明人： Hiroshi Otori , Hiroki Fujisawa , Minoru Ebihara , Seiji Narui , Masanori Isoda , Akira Ohta
IPC分类号： G11C700
CPC分类号： G11C29/70 , G11C5/025 , G11C5/063
摘要： Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.
摘要翻译：每个具有用于根据阈值电压差存储信息的电可编程电保险丝和地址比较器的排气单元（UNITb）设置在第二区域中，并且每个具有激光熔丝和地址比较器的释放单元（UNITa）设置在第一个区域。两个区域沿着每个比较器的地址信号布线彼此相邻，并且地址信号布线线性布置。即使电保险丝和激光熔丝被共存用于释放地址存储，也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异，并且可以从布局的观点最大限度地抑制片上占用面积的增加。

73. 发明授权

US06545902B2 Ferroelectric memory device 有权
公开(公告)号：US06545902B2
公开(公告)日：2003-04-08
申请号：US09987590
申请日：2001-11-15
申请人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
发明人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.

74. 发明授权

US06538924B2 Semiconductor integrated circuit 有权
公开(公告)号：US06538924B2
公开(公告)日：2003-03-25
申请号：US09866628
申请日：2001-05-30
申请人： Chiaki Dono , Tsugio Takahashi , Hiroki Fujisawa , Masanori Isoda
发明人： Chiaki Dono , Tsugio Takahashi , Hiroki Fujisawa , Masanori Isoda
IPC分类号： G11C1400
CPC分类号： G11C29/789 , G11C14/00 , G11C16/0441 , G11C2216/10
摘要： In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.

75. 发明授权

US06201728B1 Dynamic RAM, semiconductor storage device, and semiconductor integrated circuit device 有权
标题翻译：动态RAM，半导体存储器件和半导体集成电路器件
公开(公告)号：US06201728B1
公开(公告)日：2001-03-13
申请号：US09101009
申请日：1999-02-08
申请人： Seiji Narui , Osamu Nagashima , Masatoshi Hasegawa , Hiroki Fujisawa , Shinichi Miyatake , Tsuyuki Suzuki , Yasunobu Aoki , Tsutom Takahashi , Kazuhiko Kajigaya
发明人： Seiji Narui , Osamu Nagashima , Masatoshi Hasegawa , Hiroki Fujisawa , Shinichi Miyatake , Tsuyuki Suzuki , Yasunobu Aoki , Tsutom Takahashi , Kazuhiko Kajigaya
IPC分类号： G11C1124
CPC分类号： G11C11/4091 , G11C7/065 , H01L27/10805
摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.
摘要翻译：产生相对于电源电压具有差异的第一内部电压，该差基本上等于动态存储单元的地址选择MOSFET的阈值电压。第一电压作为其高级侧的工作电压被提供给读出放大器。产生相对于电路接地电位具有预定差异的第二内部电压。第二电压作为低电平侧的工作电压提供给读出放大器。通过写放大器产生具有对应于第一内部电压的高电平和对应于第二内部电压的低电平的写入信号，以将其传送到连接到动态存储单元的一对互补数据线。高电平，例如表示选择电平和低电平的电源电压，例如指示非选择电平的电路接地电平被提供给连接到动态存储器单元的字线。

76. 发明授权

US08901781B2 Prevention of the propagation of power supply noise from one output circuit to another in a semiconductor device 有权
标题翻译：在半导体器件中防止电源噪声从一个输出电路传播到另一个输出电路
公开(公告)号：US08901781B2
公开(公告)日：2014-12-02
申请号：US12453772
申请日：2009-05-21
申请人： Takenori Sato , Hiroki Fujisawa
发明人： Takenori Sato , Hiroki Fujisawa
IPC分类号： H01B7/30 , H02J1/00
CPC分类号： H02J1/00 , Y10T307/305
摘要： A semiconductor device is disclosed. A first power supply wiring for connecting between a first output circuit consisting of a predetermined number of output circuits and a first power supply pad which corresponds to the first output circuit, is connected via a resistor with a second power supply wiring for connecting between a second output circuit consisting of a predetermined number of output circuit and a second power supply pad which corresponds to the second output circuit. Thus, power supply noise that is to be propagated to certain output circuits via in-chip output power supply wirings can be reduced.
摘要翻译：公开了一种半导体器件。用于连接由预定数量的输出电路组成的第一输出电路和对应于第一输出电路的第一电源焊盘之间的第一电源布线经由电阻器与第二电源布线连接，用于连接第二电源布线输出电路由预定数量的输出电路和对应于第二输出电路的第二电源焊盘构成。因此，可以减少通过片上输出电源布线传播到某些输出电路的电源噪声。

77. 发明授权

US08537626B2 Semiconductor device and method of controlling the same 失效
标题翻译：半导体装置及其控制方法
公开(公告)号：US08537626B2
公开(公告)日：2013-09-17
申请号：US13317595
申请日：2011-10-24
申请人： Hiroki Fujisawa , Kazuhisa Ureshino
发明人： Hiroki Fujisawa , Kazuhisa Ureshino
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F2213/0038 , G11C7/109 , G11C11/40611 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4096
摘要： A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.
摘要翻译：半导体器件包括经由检测电路连接到存储单元阵列的数据输入/输出电路，以及控制对存储单元阵列的访问的访问控制电路。访问控制电路包括：第一信号单元，输出用于激活或停用字线的第一信号; 第二信号单元，输出用于激活或去激活位线和所述感测电路的第二信号; 第三信号单元，输出用于启动或停止向感测电路提供过驱动电压的第三信号; 以及输出用于停用字线的第四信号的第四信号单元。根据外部电压的大小来确定第三信号保持激活的周期。在第四信号单元中，独立于外部电压的大小来确定产生第四信号的定时。

78. 发明授权

US08493110B2 Device including a clock generation circuit and a method of generating a clock signal 有权
公开(公告)号：US08493110B2
公开(公告)日：2013-07-23
申请号：US13184273
申请日：2011-07-15
申请人： Yoshio Mizukane , Hiroki Fujisawa
发明人： Yoshio Mizukane , Hiroki Fujisawa
IPC分类号： H03L7/06
CPC分类号： H03L7/06 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03L7/0812 , H03L7/10
摘要： A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.

79. 发明授权

US08198911B2 Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit 有权
标题翻译：用于半导体器件的输出电路，具有输出电路的半导体器件以及调整输出电路特性的方法
公开(公告)号：US08198911B2
公开(公告)日：2012-06-12
申请号：US12883563
申请日：2010-09-16
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： H03K17/16 , H03K19/003 , H03K3/00 , H03B1/00
CPC分类号： H03H11/28 , G01R31/31713 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , H03K19/0005
摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
摘要翻译：减少校准输出电路所需的电路规模，并减少校准操作所需的时间。本发明包括连接到数据引脚的第一输出缓冲器和第二输出缓冲器以及连接到校准引脚的校准电路。第一输出缓冲器和第二输出缓冲器包括多个单元缓冲器。单元缓冲器具有相互相同的电路结构。利用这种布置，基于使用校准电路的校准操作，可以将第一输出缓冲器和第二输出缓冲器的阻抗设置为共同的。因此，可以减少校准操作所需的电路规模和校准操作所需的时间。

80. 发明申请

US20120120754A1 Semiconductor device including latency counter 有权
标题翻译：半导体器件包括延迟计数器
公开(公告)号：US20120120754A1
公开(公告)日：2012-05-17
申请号：US13317598
申请日：2011-10-24
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G11C8/18 , H03L7/00
CPC分类号： G11C8/18 , G11C7/109 , G11C11/4076 , G11C2207/2272 , H03L7/00
摘要： For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.
摘要翻译：例如，半导体器件包括第一延迟计数器，其选择是否对内部命令信号给出奇数周期等待时间; 以及第二延迟计数器，其以两个周期的间隔给出内部命令信号的等待时间。延迟计数器串联连接。由于用于设置等待时间的控制信息中的比特数比可设置的等待时间的类型小，所以可以减少配线密度。

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