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1. 发明专利

JP2005171651A Steel frame house 审中-公开
标题翻译：钢框架
公开(公告)号：JP2005171651A
公开(公告)日：2005-06-30
申请号：JP2003414331
申请日：2003-12-12
申请人： Tsugio Takahashi , 次男高橋
发明人： TAKAHASHI TSUGIO
IPC分类号： E04B1/64 , E04B1/24 , E04B1/30
摘要： PROBLEM TO BE SOLVED: To provide a steel frame house which has a simple structure, excels in workability, earthquake resistance and fireproof performance, and prevents internal dew condensation of a hollow steel frame.
SOLUTION: The steel frame house includes the hollow steel frame (a column 10, a beam 20), the inside of which is filled with one or more materials of a gypsum powder, a stone flour, a cement powder and a baked sand, and is filled with a mixture of a gypsum, a sand and a water, or a mixture of the gypsum and the water. The inside of the hollow steel frame is filled with a cement-based foamed mortar and/or a foamed concrete, or a foamed urethane. The filling work is carried out in a state that a cylindrical member 50 is erected inside the column 10.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种结构简单，操作性，抗震性和耐火性能优异的钢框架房，防止中空钢框架的内部结露。钢框架房屋包括中空钢框架（柱10，梁20），其内部填充有一种或多种石膏粉，石粉，水泥粉和烘烤的材料沙子，并填充有石膏，沙子和水的混合物，或石膏和水的混合物。中空钢框架的内部填充有水泥基发泡砂浆和/或发泡混凝土或泡沫聚氨酯。填充工作是在柱10内竖立圆柱形构件50的状态下进行的。（C）2005年，JPO＆NCIPI

2. 发明专利

JP2005120757A Steel frame house 审中-公开
标题翻译：钢框架
公开(公告)号：JP2005120757A
公开(公告)日：2005-05-12
申请号：JP2003358450
申请日：2003-10-17
申请人： Tsugio Takahashi , 次男高橋
发明人： TAKAHASHI TSUGIO
IPC分类号： E04B1/30 , E04C3/29 , E04C3/293 , E04C3/32
摘要： PROBLEM TO BE SOLVED: To provide a steel frame house having a simple structure, excellent construction property, and excellent earthquake and fire resistance and capable of preventing dew condensation inside a hollow steel frame.
SOLUTION: One kind or two kinds or more of any of gypsum powder/stone dust/cement powder/burnt sand are filled into the inside of the hollow steel frame (a column 10, a beam 20). Gypsum, sand, and water or gypsum and water are mixed together and are filled into the inside of the hollow steel frame. Cement foaming mortar and/or foaming concrete are filled into the inside of the hollow steel frame. Foaming urethane is filled into the inside of the hollow steel frame. Filling work is performed into the inside of the column 10 in the condition that a cylindrical member 50 has been erected.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种结构简单，施工性能优良，耐震和耐火性优异并且能够防止中空钢框架内的结露的钢框架房。解决方案：将一种或两种以上的任何石膏粉/石粉/水泥粉/烧砂填充到中空钢框架（柱10，梁20）的内部。将石膏，砂，水或石膏和水混合在一起并填充到中空钢框架的内部。水泥发泡砂浆和/或发泡混凝土填充到中空钢框架的内部。发泡聚氨酯填充到中空钢框架的内部。在竖立有圆柱形构件50的情况下，在塔10的内部进行填充作业。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPS54146095A Automatic lathe 失效
标题翻译：自动拉链
公开(公告)号：JPS54146095A
公开(公告)日：1979-11-14
申请号：JP5471978
申请日：1978-05-08
申请人： Tsugio Takahashi
发明人： TAKAHASHI TSUGIO
IPC分类号： B23B7/12 , B23B7/00

4. 发明专利

JP2005105648A Steel frame house 审中-公开
标题翻译：钢框架
公开(公告)号：JP2005105648A
公开(公告)日：2005-04-21
申请号：JP2003339718
申请日：2003-09-30
申请人： Tsugio Takahashi , 次男高橋
发明人： TAKAHASHI TSUGIO
IPC分类号： E04B1/30
摘要： PROBLEM TO BE SOLVED: To provide a steel frame house having a simple structure, superior in workability, and superior in aseismatic and fire resistant performance; and a steel frame structure capable of preventing inside condensation of a hollow steel frame.
SOLUTION: Any one kind or two ore more kinds of gypsum powder, stone dust, cement powder, and burnt sand, are filled inside the hollow steel frame (a column 10 and a beam 20). Gypsum, sand and water or the gypsum and the water are mixed together, and are filled inside the hollow steel frame. Cement type foaming mortar and/or foaming concrete are filled inside the hollow steel frame. Urethane foam is filled inside the hollow steel frame. Filling work is performed in a state of arranging vertical reinforcements inside the hollow steel frame.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种结构简单，加工性优异，抗震性和耐火性能优异的钢框架房; 以及能够防止中空钢框架内部冷凝的钢框架结构。
解决方案：中空钢框架（柱10和梁20）内装满任何一种或两种以上的石膏粉，石灰，水泥粉和烧砂。将石膏，砂和水或石膏和水混合在一起，并填充在中空钢框架的内部。水泥型发泡砂浆和/或发泡混凝土填充在中空钢框架内。聚氨酯泡沫填充在中空钢框架内。在中空钢框架内部设置垂直加强件的状态下进行填充加工。版权所有（C）2005，JPO＆NCIPI

5. 发明申请

US20120243877A1 OPTICAL TRANSCEIVING SYSTEM WITH FRAME SYNCHRONIZATION AND OPTICAL RECEIVING APPARATUS 有权
标题翻译：具有帧同步和光接收装置的光收发系统
公开(公告)号：US20120243877A1
公开(公告)日：2012-09-27
申请号：US13425625
申请日：2012-03-21
申请人： Tsugio TAKAHASHI
发明人： Tsugio TAKAHASHI
IPC分类号： H04B10/00 , H04B10/06
CPC分类号： H04B10/40 , H04B10/69 , H04L7/048
摘要： An optical receiving apparatus with frame synchronization technology which makes it easy to activate a frame synchronization established state even if bit errors are produced over a transmission link. The apparatus includes: an optoelectrical converting circuit; a pre-stage synchronizing word detecting circuit; a decoder; a post-stage frame synchronization detecting circuit; and a receiver frame synchronization display output circuit.
摘要翻译：具有帧同步技术的光接收装置，即使在传输链路上产生位错误，也容易激活帧同步建立状态。该装置包括：光电转换电路; 一个前级同步字检测电路; 解码器后级帧同步检测电路; 和接收机帧同步显示输出电路。

6. 发明申请

US20080025346A1 Method and device for synchronizing and multiplexing asynchronous signals 审中-公开
标题翻译：用于同步和复用异步信号的方法和设备
公开(公告)号：US20080025346A1
公开(公告)日：2008-01-31
申请号：US11882002
申请日：2007-07-30
申请人： Tsugio Takahashi , Koichi Usami
发明人： Tsugio Takahashi , Koichi Usami
IPC分类号： H04J3/06
CPC分类号： H04J3/0623 , H04J3/0685 , H04J3/1611
摘要： A method and an apparatus for synchronizing and multiplexing asynchronous signals are presented that enable the plurality of asynchronous signals to be processed without increasing the scale of circuitry. Clock phase absorption sections allow respective asynchronous STM-N signals to switch to a system clock signal. In accordance with the system clock signal, a MSOH termination section, a pointer reception section and a memory section carry out MSOH termination processing, frame phase absorption processing and the like in serial on the asynchronous STM-N signals. Synchronous signals thus generated after frame phase absorption are multiplexed through processing of changing pointer values and the like by a pointer transmission section.
摘要翻译：提出了一种用于同步和复用异步信号的方法和装置，其能够在不增加电路规模的情况下处理多个异步信号。时钟相位吸收部分允许相应的异步STM-N信号切换到系统时钟信号。根据系统时钟信号，MSOH终端部分，指针接收部分和存储部分在异步STM-N信号上串行执行MSOH终止处理，帧相位吸收处理等。在帧相位吸收之后产生的同步信号通过指针传输部分改变指针值等进行复用。

7. 再颁专利

USRE38944E1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

8. 发明授权

US06538912B2 Semiconductor device 有权
公开(公告)号：US06538912B2
公开(公告)日：2003-03-25
申请号：US10139330
申请日：2002-05-07
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

9. 发明授权

US06400596B2 Semiconductor memory device using open data line arrangement 有权
标题翻译：半导体存储器件采用开放数据线布置
公开(公告)号：US06400596B2
公开(公告)日：2002-06-04
申请号：US09725107
申请日：2000-11-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
摘要翻译：当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线内存阵列因此，提供了根据本发明的半导体器件。在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统放置即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

10. 发明授权

US5966341A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

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