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1. 发明授权

US06538924B2 Semiconductor integrated circuit 有权
公开(公告)号：US06538924B2
公开(公告)日：2003-03-25
申请号：US09866628
申请日：2001-05-30
申请人： Chiaki Dono , Tsugio Takahashi , Hiroki Fujisawa , Masanori Isoda
发明人： Chiaki Dono , Tsugio Takahashi , Hiroki Fujisawa , Masanori Isoda
IPC分类号： G11C1400
CPC分类号： G11C29/789 , G11C14/00 , G11C16/0441 , G11C2216/10
摘要： In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.

2. 发明授权

US06667905B2 Semiconductor integrated circuit 有权
公开(公告)号：US06667905B2
公开(公告)日：2003-12-23
申请号：US10337322
申请日：2003-01-07
申请人： Chiaki Dono , Tsugio Takahashi , Hiroki Fujisawa , Masanori Isoda
发明人： Chiaki Dono , Tsugio Takahashi , Hiroki Fujisawa , Masanori Isoda
IPC分类号： G11C1400
CPC分类号： G11C29/789 , G11C14/00 , G11C16/0441 , G11C2216/10
摘要： In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.

3. 发明授权

US08254153B2 Semiconductor memory device having pad electrodes arranged in plural rows 有权
标题翻译：具有排列成多列的焊盘电极的半导体存储器件
公开(公告)号：US08254153B2
公开(公告)日：2012-08-28
申请号：US12923168
申请日：2010-09-07
申请人： Chiaki Dono , Hiroki Fujisawa
发明人： Chiaki Dono , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C5/02
摘要： To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area.
摘要翻译：为了包括第一存储单元阵列区域和第二存储单元阵列区域，布置在这些存储单元阵列区域之间的外围电路区域，布置在第一存储单元阵列区域和外围电路区域之间的第一焊盘行和第二焊盘行布置在第二存储单元阵列区域和外围电路区域之间。没有外围电路基本上布置在第一存储单元阵列区域和第一焊盘行之间以及第二存储单元阵列区域和第二焊盘行之间。通过这种布置，通过使用形成在具有较低电阻的上层中的布线，可以在更短的距离内连接存储单元阵列区域和预定焊盘，并且可以将电力稳定地提供给存储单元阵列区域。

4. 发明授权

US06765815B2 Semiconductor memory device having a main word-line layer disposed above a column selection line layer 有权
标题翻译：具有设置在列选择线层上方的主字线层的半导体存储器件
公开(公告)号：US06765815B2
公开(公告)日：2004-07-20
申请号：US10447893
申请日：2003-05-29
申请人： Hiroki Fujisawa , Koji Arai , Chiaki Dono
发明人： Hiroki Fujisawa , Koji Arai , Chiaki Dono
IPC分类号： G11C506
CPC分类号： H01L27/10882 , G11C5/025 , G11C8/14 , G11C11/4087 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10885 , H01L27/10891
摘要： The present invention discloses a semiconductor memory device having a multilevel interconnection structure with no conventional limitation on the number of lines. The semiconductor memory device has a multilevel interconnection structure in which column selection lines extending in the Y direction and main word lines extending in the X direction are arranged in different layers. The layer including the column selection lines is disposed under the layer including the main word lines. In the structure, in sub-word driver areas intersecting the X direction, the main word lines are arranged in a top layer and sub-word selection lines are arranged in a layer lower than the top layer. The lower layer includes a pattern of islands. According to this interconnection structure, the number of islands can be reduced. Consequently, a plurality of power lines can be arranged between the adjacent main word lines in the sub-word driver areas.
摘要翻译：本发明公开了一种具有多层互连结构的半导体存储器件，对线数量没有任何常规限制。半导体存储器件具有多层互连结构，其中沿Y方向延伸的列选择线和沿X方向延伸的主字线布置在不同的层中。包括列选择线的层被布置在包括主字线的层之下。在该结构中，在与X方向相交的子字驱动器区域中，主字线布置在顶层中，子字选择线布置在比顶层低的层中。下层包括岛屿图案。根据该互连结构，可以减少岛数。因此，可以在子字驱动器区域中的相邻主字线之间布置多条电源线。

5. 发明申请

US20110058401A1 Semiconductor memory device having pad electrodes arranged in plural rows 有权
标题翻译：具有排列成多列的焊盘电极的半导体存储器件
公开(公告)号：US20110058401A1
公开(公告)日：2011-03-10
申请号：US12923168
申请日：2010-09-07
申请人： Chiaki Dono , Hiroki Fujisawa
发明人： Chiaki Dono , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C5/02
摘要： To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area.
摘要翻译：为了包括第一存储单元阵列区域和第二存储单元阵列区域，布置在这些存储单元阵列区域之间的外围电路区域，布置在第一存储单元阵列区域和外围电路区域之间的第一焊盘行和第二焊盘行布置在第二存储单元阵列区域和外围电路区域之间。没有外围电路基本上布置在第一存储单元阵列区域和第一焊盘行之间以及第二存储单元阵列区域和第二焊盘行之间。通过这种布置，通过使用形成在具有较低电阻的上层中的布线，可以在更短的距离内连接存储单元阵列区域和预定焊盘，并且可以将电力稳定地提供给存储单元阵列区域。

6. 发明授权

US08134882B2 Semiconductor device including an anti-fuse element 有权
标题翻译：包括反熔丝元件的半导体器件
公开(公告)号：US08134882B2
公开(公告)日：2012-03-13
申请号：US12621167
申请日：2009-11-18
申请人： Chiaki Dono
发明人： Chiaki Dono
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/16 , G11C17/165 , G11C29/027 , G11C29/785
摘要： A semiconductor device includes a first high potential power supply, a second low potential power supply, a third power supply having a potential higher than the first, a fourth power supply having a potential more negative than the second, and an anti-fuse element having a node at each end, one of which is connected to the fourth power supply. A driver transistor has a source connected to the third power supply, a gate connected to a control node and a drain connected to one end of the anti-fuse element. A decoding circuit includes a load transistor connected between the third power supply and the control node and at least one selection transistor connected between the second power supply and the control node. A decision circuit is connected to the first and second power supplies. The decision circuit decides the resistance value of the anti-fuse element. The anti-fuse element is rendered electrically conductive in response to activation of the driver transistor as selected by the decoding circuit. The decision circuit decides whether or not the anti-fuse element has been rendered electrically conductive.
摘要翻译：半导体器件包括第一高电位电源，第二低电位电源，具有高于第一电位的第一电源，具有比第二电位更负的电位的第四电源，以及具有每个端部的节点，其中一个连接到第四电源。驱动晶体管具有连接到第三电源的源极，连接到控制节点的栅极和连接到反熔丝元件的一端的漏极。解码电路包括连接在第三电源和控制节点之间的负载晶体管和连接在第二电源和控制节点之间的至少一个选择晶体管。判定电路连接到第一和第二电源。判定电路决定反熔丝元件的电阻值。响应于由解码电路选择的驱动晶体管的激活，反熔丝元件被导电。判定电路判定反熔丝元件是否已导电。

7. 发明授权

US07742356B2 Semiconductor memory device having a refresh cycle changing circuit 有权
标题翻译：具有刷新周期改变电路的半导体存储器件
公开(公告)号：US07742356B2
公开(公告)日：2010-06-22
申请号：US11987767
申请日：2007-12-04
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.
摘要翻译：半导体存储器件包括：第一刷新周期改变电路，其根据自刷新模式改变刷新周期，而不影响根据自刷新模式的刷新周期;以及第二刷新周期改变电路，其改变刷新根据自刷新模式循环，而不会根据自动刷新模式对刷新周期产生影响。以这种方式，根据本发明，可以独立地控制根据自刷新模式的刷新周期和根据自刷新模式的刷新周期。因此，可以执行考虑每个模式的特性的刷新操作。

8. 发明申请

US20100090675A1 Semiconductor device and test method therefor 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US20100090675A1
公开(公告)日：2010-04-15
申请号：US12292432
申请日：2008-11-19
申请人： Chiaki Dono , Atsushi Fujikawa
发明人： Chiaki Dono , Atsushi Fujikawa
IPC分类号： G05F3/16 , G01R31/00
CPC分类号： G01R31/31723 , G11C29/02 , G11C29/021 , G11C29/1201 , G11C29/48
摘要： Disclosed is a semiconductor device including internal power supply generating circuits for generating internal power supplies and data terminals via which data signals are output or input/output. The internal power supply monitor terminals are in common use with the data terminals. The semiconductor device also includes selection circuits for selecting, by a test control signal, whether or not output voltages of the internal power supply generating circuits are to be output to the data terminals.
摘要翻译：公开了一种半导体器件，包括用于产生内部电源的内部电源产生电路和数据信号被输出或输出的数据端子。内部电源监视器端子与数据终端通用。半导体器件还包括选择电路，用于通过测试控制信号选择内部电源发生电路的输出电压是否被输出到数据终端。

9. 发明申请

US20080151659A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20080151659A1
公开(公告)日：2008-06-26
申请号：US11959253
申请日：2007-12-18
申请人： Kazuki Sakuma , Jun Suzuki , Chiaki Dono
发明人： Kazuki Sakuma , Jun Suzuki , Chiaki Dono
IPC分类号： G11C7/00 , G11C29/00 , G11C8/00
CPC分类号： G11C29/40 , G11C5/04 , G11C29/802
摘要： A semiconductor memory device includes at least one memory bank. Each memory bank includes: memory units that output data in response to a burst read command; a selector section that sequentially outputs the data output from the memory units in accordance with a select signal; a comparator section that compares the data sequentially output from the selector section with reference data sequentially input, outputs a comparison result indicating normal when the data output from the selector section matches with the reference data, and outputs a comparison result indicating abnormal when the data output from the selector section does not match with the reference data; and a reduction result storage section that stores, as a reduction result of the memory bank, a value indicating normal when comparison results sequentially output from the comparator section all indicate normal, and a value indicating abnormal when any one of the comparison results indicates abnormal.
摘要翻译：半导体存储器件包括至少一个存储体。每个存储体包括：响应突发读命令输出数据的存储器单元; 选择器部分，其根据选择信号依次输出从存储器单元输出的数据; 将从选择器部顺序地输出的数据与依次输入的参考数据进行比较的比较器部，当从选择部输出的数据与参考数据匹配时，输出表示正常的比较结果，并输出指示异常的比较结果从选择器部分与参考数据不匹配; 以及减少结果存储部分，当从比较器部分顺序输出的比较结果全部表示正常时，作为存储体的缩小结果，存储指示正常的值，以及当比较结果指示异常时表示异常的值。

10. 发明授权

US06845043B2 Method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled 失效
标题翻译：验证半导体集成电路装置的方法，其可以在组装之后充分评估非破坏性熔丝模块的可靠性
公开(公告)号：US06845043B2
公开(公告)日：2005-01-18
申请号：US10310623
申请日：2002-12-05
申请人： Chiaki Dono
发明人： Chiaki Dono
IPC分类号： G01R31/30 , G01R31/28 , G11C11/401 , G11C29/00 , G11C29/02 , G11C29/04 , G11C16/06
CPC分类号： G11C29/789 , G11C29/02 , G11C29/027 , G11C29/835
摘要： A method of verifying a semiconductor integrated circuit apparatus includes (a) providing a semiconductor integrated circuit apparatus including: a first transistor which has a floating gate in which a potential is floated and to which data is written; a second transistor which has a floating gate connected together with the floating gate and reads out the data written to the first transistor; and a control gate unit, which is coupled to the floating gate, controlling an operation of reading out the data of the second transistor; (b) comparing a first data outputted through the second transistor when a first potential is applied to the control gate unit with a second data outputted through the second transistor when a second potential is applied to the control gate unit to generate a comparison result; and (c) verifying the data written to the floating gate based on the comparison result.
摘要翻译：一种验证半导体集成电路装置的方法包括：（a）提供一种半导体集成电路装置，包括：第一晶体管，其具有浮置栅极，其中浮置电位并写入数据; 第二晶体管，其具有与浮置栅极连接的浮置栅极，并读出写入第一晶体管的数据; 以及耦合到所述浮动栅极的控制栅极单元，控制读出所述第二晶体管的数据的操作; （b）当将第二电位施加到控制栅单元以产生比较结果时，将第一电位施加到控制栅单元上的第一数据与通过第二晶体管输出的第二数据进行比较; 和（c）基于比较结果验证写入浮动门的数据。

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