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1. 发明授权

US06545902B2 Ferroelectric memory device 有权
公开(公告)号：US06545902B2
公开(公告)日：2003-04-08
申请号：US09987590
申请日：2001-11-15
申请人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
发明人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.

2. 发明授权

US06330178B1 Ferroelectric memory device 有权
标题翻译：铁电存储器件
公开(公告)号：US06330178B1
公开(公告)日：2001-12-11
申请号：US09558104
申请日：2000-04-25
申请人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
发明人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge sharing between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.
摘要翻译：由于铁电存储器件不能采用在DRAM中广泛使用的VCC / 2预充电方案，其阵列噪声和功耗很大。此外，由于其疲劳和压印，铁电电容器的特性劣化。为了避免这种情况，数据线对被预充电到两个电压VCC和VSS。结果，存储单元阵列MCA中的数据线上的电压以VCC / 2为中心对称地变化，从而减少阵列噪声。此外，当基于不同预充电电压的数据线之间的电荷共享来执行早期感测和早期预充电操作时，可以降低功耗。此外，当为各个数据线切换预充电电压时，在存储单元中的铁电电容器中交替执行反向和非反向极化以抑制其疲劳和压印。

3. 发明授权

US6097623A Ferroelectric memory device having two columns of memory cells precharged to separate voltages 有权
标题翻译：具有预先充电以分离电压的两列存储器单元的铁电存储器件
公开(公告)号：US6097623A
公开(公告)日：2000-08-01
申请号：US125545
申请日：1998-08-28
申请人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
发明人： Takeshi Sakata , Tomonori Sekiguchi , Hiroki Fujisawa , Katsutaka Kimura , Masanori Isoda , Kazuhiko Kajigaya
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C11/22
摘要： Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge share between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.
摘要翻译： PCT No.PCT / JP96 / 00464 Sec。 371日期1998年8月28日 102（e）1998年8月28日PCT PCT 1996年2月28日PCT公布。公开号WO97 / 32311 日期1997年9月4日由于铁电存储器件不能采用DRAM广泛使用的VCC / 2预充电方案，其阵列噪声和功耗很大。此外，由于其疲劳和压印，铁电电容器的特性劣化。为了避免这种情况，数据线对被预充电到两个电压VCC和VSS。结果，存储单元阵列MCA中的数据线上的电压以VCC / 2为中心对称地变化，从而减少阵列噪声。此外，当基于不同预充电电压的数据线之间的电荷共享来执行早期感测和早期预充电操作时，可以降低功耗。此外，当为各个数据线切换预充电电压时，在存储单元中的铁电电容器中交替执行反向和非反向极化以抑制其疲劳和压印。

4. 发明授权

US06538912B2 Semiconductor device 有权
公开(公告)号：US06538912B2
公开(公告)日：2003-03-25
申请号：US10139330
申请日：2002-05-07
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

5. 发明授权

US06400596B2 Semiconductor memory device using open data line arrangement 有权
标题翻译：半导体存储器件采用开放数据线布置
公开(公告)号：US06400596B2
公开(公告)日：2002-06-04
申请号：US09725107
申请日：2000-11-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
摘要翻译：当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线内存阵列因此，提供了根据本发明的半导体器件。在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统放置即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

6. 发明申请

US20070297257A1 Semiconductor memory device capable of canceling out noise development 审中-公开
标题翻译：能够消除噪声发展的半导体存储器件
公开(公告)号：US20070297257A1
公开(公告)日：2007-12-27
申请号：US11889902
申请日：2007-08-17
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.
摘要翻译：动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。电源线以网格形式提供，包括字驱动器上方的一部分。

7. 发明授权

US06944080B2 Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors 有权
标题翻译：动态随机存取存储器（DRAM）能够消除在存储单元电容器的平板电极中产生的互补噪声
公开(公告)号：US06944080B2
公开(公告)日：2005-09-13
申请号：US10938794
申请日：2004-09-13
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.
摘要翻译：一种动态RAM，包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到所述多个动态存储单元的输入/输出端的多个互补位线对，并且被放置在与以及根据操作定时信号提供工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。在动态RAM中，与以感测放大器阵列为中心的两侧的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接而通过使用公共电极的布线来确保读出放大器阵列中的电路连接。

8. 发明授权

US06807120B2 Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors 有权
标题翻译：动态随机存取存储器（DRAM）能够消除在存储单元电容器的平板电极中产生的互补噪声
公开(公告)号：US06807120B2
公开(公告)日：2004-10-19
申请号：US10309180
申请日：2002-12-04
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C702
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive layer being over the first region; a second conductive layer being over the second region; and a connecting layer, being over the third region, which electrically connects the first conductive layer with the second conductive layer. The sense amplifiers amplify differences in voltage between the first bit lines and the second bit lines. Each of the first memory cells includes a first storage capacitor having an electrode connected to the first conductive layer. Each of the second memory cells includes a second storage capacitor having an electrode connected to the second conductive layer.
摘要翻译：半导体器件包括具有第一位线，第一字线和第一存储器单元的第一区域; 具有第二位线的第二区域，第二字线和第二存储器单元; 具有放置在所述第一区域和所述第二区域之间的读出放大器的第三区域; 在所述第一区域之上的第一导电层; 在所述第二区域上方的第二导电层; 以及连接层，其在第三区域之上，其将第一导电层与第二导电层电连接。感测放大器放大第一位线和第二位线之间的电压差。每个第一存储单元包括具有连接到第一导电层的电极的第一存储电容器。每个第二存储单元包括具有连接到第二导电层的电极的第二存储电容器。

9. 发明授权

US06671198B2 Semiconductor device 有权
公开(公告)号：US06671198B2
公开(公告)日：2003-12-30
申请号：US10354122
申请日：2003-01-30
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C506
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

10. 发明申请

US20080002448A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20080002448A1
公开(公告)日：2008-01-03
申请号：US11896802
申请日：2007-09-06
申请人： Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
发明人： Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
IPC分类号： G11C5/06
CPC分类号： G11C7/02 , G11C5/06 , G11C5/063 , G11C8/08 , G11C8/14 , G11C11/408 , G11C11/4085 , G11C11/4096 , G11C11/4097 , H01L27/0207 , H01L27/10814 , H01L27/10882
摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.
摘要翻译：在追求微型制造的大规模集成DRAM中，数据线字线耦合电容在配对数据线之间不平衡。数据线字线的不平衡意味着当数据线经受放大时产生大的噪声，这极有可能引起数据线上非常小的信号的恶化和数据的错误放大。连接到连接到一个数据线的多个存储单元的多个字线中的一个或几个字线交替地连接到布置在存储器阵列的相对侧上的子字驱动器阵列。当数据线被放大时，正和负字线噪声分量在子字驱动器中彼此抵消，从而可以减小字线噪声。因此，可以防止由读出放大器读出的信号劣化，从而提高存储器操作的可靠性。

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