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1. 发明授权

US06563759B2 Semiconductor memory device 有权
公开(公告)号：US06563759B2
公开(公告)日：2003-05-13
申请号：US09871911
申请日：2001-06-04
申请人： Hideharu Yahata , Masashi Horiguchi , Hiroki Fujisawa , Tsugio Takahashi , Masayuki Nakamura
发明人： Hideharu Yahata , Masashi Horiguchi , Hiroki Fujisawa , Tsugio Takahashi , Masayuki Nakamura
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4082 , G11C11/4087
摘要： In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).

2. 发明申请

US20050073895A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050073895A1
公开(公告)日：2005-04-07
申请号：US10636558
申请日：2003-08-08
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

3. 发明申请

US20050237839A1 Semiconductor memory device 有权
公开(公告)号：US20050237839A1
公开(公告)日：2005-10-27
申请号：US11168291
申请日：2005-06-29
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

4. 发明授权

US06851017B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06851017B2
公开(公告)日：2005-02-01
申请号：US10174962
申请日：2002-06-20
申请人： Masashi Horiguchi , Shigeki Ueda , Hideharu Yahata
发明人： Masashi Horiguchi , Shigeki Ueda , Hideharu Yahata
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/04 , H01L27/10 , G06F12/00
CPC分类号： G11C29/783 , G11C11/406
摘要： The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiving the internal address signal therein and determining whether the corresponding address corresponds to an address for a defective word line of a plurality of normal word lines, and an address counter for generating refresh address signals for sequentially refreshing the plurality of normal word lines and redundant word lines. The redundant judgment circuit is deactivated upon refresh.
摘要翻译：本发明提供了能够缩短刷新周期时间并降低刷新时的功耗的半导体存储器。半导体存储器包括用于产生每个内部地址信号的地址输入电路，用于在其中接收内部地址信号的冗余判断电路，并确定对应的地址是否对应于多个正常字线的有缺陷字线的地址，以及地址计数器，用于产生用于顺序地刷新多个正常字线和冗余字线的刷新地址信号。冗余判断电路在刷新时被停用。

5. 发明授权

US06563755B2 Semiconductor memory device 失效
公开(公告)号：US06563755B2
公开(公告)日：2003-05-13
申请号：US09986082
申请日：2001-11-07
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshinobu Nakagome , Yoshikazu Saitoh
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshinobu Nakagome , Yoshikazu Saitoh
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to read or write stored information or information to be stored and a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation before or after such first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells are not mutually affected in the first memory operation and the second memory operation or the refresh operation.

6. 发明授权

US07203116B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07203116B2
公开(公告)日：2007-04-10
申请号：US11448016
申请日：2006-06-07
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

7. 发明授权

US07082063B2 Semiconductor memory device 有权
公开(公告)号：US07082063B2
公开(公告)日：2006-07-25
申请号：US11168291
申请日：2005-06-29
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

8. 发明授权

US06928017B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06928017B2
公开(公告)日：2005-08-09
申请号：US10636558
申请日：2003-08-08
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器的存储器操作的指令，每个存储器单元需要用于周期性地保持存储器信息的刷新操作或者将其写入其中，执行与之前的存储器操作不同的基于寻址的自主刷新操作或者在内存操作之后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

9. 发明授权

US06625079B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06625079B2
公开(公告)日：2003-09-23
申请号：US10175301
申请日：2002-06-20
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the column address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器和根据列地址信号转换检测器的地址信号转换检测信号独立地执行列地址选择操作的页模式。

10. 发明申请

US20060227642A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060227642A1
公开(公告)日：2006-10-12
申请号：US11448016
申请日：2006-06-07
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译：为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作，内存操作后。伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。

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