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    • 1. 发明授权
    • Semiconductor memory including a circuit for selecting redundant memory cells
    • 半导体存储器,包括用于选择冗余存储单元的电路
    • US06563750B2
    • 2003-05-13
    • US10134521
    • 2002-04-30
    • Hiroshi OtoriHiroki FujisawaMinoru EbiharaSeiji NaruiMasanori IsodaAkira Ohta
    • Hiroshi OtoriHiroki FujisawaMinoru EbiharaSeiji NaruiMasanori IsodaAkira Ohta
    • G11C700
    • G11C29/70G11C5/025G11C5/063
    • Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.
    • 每个具有用于根据阈值电压差存储信息的电可编程电保险丝和地址比较器的排气单元(UNITb)设置在第二区域中,并且每个具有激光熔丝和地址比较器的释放单元(UNITa)设置在 第一个区域。 两个区域沿着每个比较器的地址信号布线彼此相邻,并且地址信号布线线性布置。 即使电保险丝和激光熔丝被共存用于释放地址存储,也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异, 并且可以从布局的观点最大限度地抑制片上占用面积的增加。
    • 2. 发明授权
    • Semiconductor device
    • 半导体器件
    • US06388941B2
    • 2002-05-14
    • US09903509
    • 2001-07-13
    • Hiroshi OtoriHiroki FujisawaMinoru EbiharaSeiji NaruiMasanori IsodaAkira Ohta
    • Hiroshi OtoriHiroki FujisawaMinoru EbiharaSeiji NaruiMasanori IsodaAkira Ohta
    • G11C800
    • G11C29/70G11C5/025G11C5/063
    • Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.
    • 每个具有用于根据阈值电压差存储信息的可电气可编程电保险丝和地址比较器的排气单元(UNITb)设置在第二区域中,并且每个具有激光熔丝和地址比较器的释放单元(UNITa)设置在 第一个区域。 两个区域沿着每个比较器的地址信号布线彼此相邻,并且地址信号布线线性布置。 即使电保险丝和激光熔丝被共存用于释放地址存储,也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异, 并且可以从布局的观点最大限度地抑制片上占用面积的增加。
    • 9. 发明授权
    • Logic gate circuit and digital integrated circuit
    • 逻辑门电路和数字集成电路
    • US5656956A
    • 1997-08-12
    • US590526
    • 1996-01-24
    • Akira OhtaNorio Higashisaka
    • Akira OhtaNorio Higashisaka
    • H03K17/687H03K19/0952H03K19/094
    • H03K19/0952
    • A logic gate circuit includes a resistor, a current limiting circuit, a switching transistor, and a load transistor, the source of load transistor being connected to the drain of the switching transistor, the gate of the switching transistor being connected to an input terminal, the resistor being connected between the source of and the gate of the load transistor, and the current limiting circuit being connected between the gate of the load transistor and the source of the switching transistor. By using this logic gate circuit in the low speed operating section of an LSI, the dissipation current and the chip area of the LSI can be reduced even when the gate width and the threshold voltage of the load FET are the same as those in the high speed operating section.
    • 逻辑门电路包括电阻器,限流电路,开关晶体管和负载晶体管,负载晶体管源极连接到开关晶体管的漏极,开关晶体管的栅极连接到输入端子, 电阻器连接在负载晶体管的源极和栅极之间,并且限流电路连接在负载晶体管的栅极和开关晶体管的源极之间。 通过在LSI的低速工作部中使用该逻辑门电路,即使当负载FET的栅极宽度和阈值电压与高电平相同时,LSI的耗散电流和芯片面积也可以减小 高速运行部分。