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71. 发明授权

US09154188B2 RF identification device with near-field-coupled antenna 有权
标题翻译：具有近场耦合天线的RF识别装置
公开(公告)号：US09154188B2
公开(公告)日：2015-10-06
申请号：US12182893
申请日：2008-07-30
申请人： Alessandro Finocchiaro , Giovanni Girlando , Giuseppe Palmisano , Giuseppe Ferla , Alberto Pagani
发明人： Alessandro Finocchiaro , Giovanni Girlando , Giuseppe Palmisano , Giuseppe Ferla , Alberto Pagani
IPC分类号： G08B23/00 , H04B5/00 , H01L23/66 , H01L25/065 , H01L23/00
CPC分类号： H04B5/00 , H01L23/66 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2223/6677 , H01L2224/48091 , H01L2225/06531 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H04B5/0031 , H04B5/0037 , H04B5/0081 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
摘要翻译： RF识别装置的实施例由标签和读取器形成。标签由具有发送和接收数据功能的处理电路和第一天线形成。读取器由控制电路和具有发送和接收数据功能的第二天线形成。处理电路由谐振电容器，调制器，整流电路，电荷泵电路和检测电路构成。标签和处理电路的天线以完全整体的形式集成在单个结构中。第一天线具有连接到整流电路的输入的端子，其输出端连接到电荷泵电路。电荷泵电路具有连接到检测电路的输出。

72. 发明授权

US06724009B2 Semiconductor integrated electronic device and corresponding manufacturing method 有权
标题翻译：半导体集成电子器件及相应的制造方法
公开(公告)号：US06724009B2
公开(公告)日：2004-04-20
申请号：US10199964
申请日：2002-07-18
申请人： Gianfranco Cerofolini , Giuseppe Ferla
发明人： Gianfranco Cerofolini , Giuseppe Ferla
IPC分类号： H01L3524
CPC分类号： H01L21/28167 , H01L29/51
摘要： A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.
摘要翻译：公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括在两个硅板之间形成的电介质氧化物层，并且其中硅板全部悬垂在氧化物层周围以限定具有基本上矩形横截面形状的底切。该方法包括以下步骤：将硅板的表面化学改变成在底切中提供的不同的官能团与其余表面中的不同的官能团; 并且将底切中提供的官能团选择性地与具有可逆还原中心和分子长度基本上等于底切宽度的有机分子反应，从而与有机分子的每个末端建立共价键。

73. 发明授权

US06278329B1 Low-noise amplifier stage with matching network 有权
标题翻译：具有匹配网络的低噪声放大器级
公开(公告)号：US06278329B1
公开(公告)日：2001-08-21
申请号：US09466573
申请日：1999-12-21
申请人： Giuseppe Palmisano , Giuseppe Ferla , Giovanni Girlando
发明人： Giuseppe Palmisano , Giuseppe Ferla , Giovanni Girlando
IPC分类号： H03F304
CPC分类号： H03F1/22 , H03F1/565 , H03F2200/294 , H03F2200/372
摘要： An amplifier stage having a first and a second transistor connected in series to each other between a first and a second reference potential line. The first transistor has a control terminal connected to an input of the amplifier stage through a first inductor, a first terminal connected to the second reference potential line through a second inductor, and a third terminal connected to a first terminal of the second transistor. The second transistor has a second terminal forming an output of the amplifier stage, and connected to the first reference potential line through a load resistor. To improve the noise figure, a matching capacitor is connected between the control terminal and the first terminal of the first transistor.
摘要翻译：具有在第一和第二参考电位线之间彼此串联连接的第一和第二晶体管的放大器级。第一晶体管具有通过第一电感器连接到放大器级的输入的控制端子，通过第二电感器连接到第二参考电位线的第一端子和连接到第二晶体管的第一端子的第三端子。第二晶体管具有形成放大器级的输出的第二端子，并通过负载电阻器连接到第一参考电位线。为了提高噪声系数，在控制端子与第一晶体管的第一端子之间连接有匹配电容器。

74. 发明授权

US5221855A Monolithic vertical-type semiconductor power device with a protection against parasitic currents 失效
标题翻译：具有防止PARASIIC电流的单片垂直型半导体功率器件
公开(公告)号：US5221855A
公开(公告)日：1993-06-22
申请号：US605447
申请日：1990-10-30
申请人： Giuseppe Ferla , Sergio Palara
发明人： Giuseppe Ferla , Sergio Palara
IPC分类号： H01L29/73 , H01L21/331 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/082 , H01L29/732
CPC分类号： H01L27/0248 , H01L27/0821
摘要： A monolithic vertical-type semiconductor power device comprises an N+ type substrate 1 over which there is superimposed an N- type epitaxial layer 2 in which there is obtained a P type isolation pocket 3. The pocket 3 contains N type regions 4, 15 and P type regions 6 which in turn contain N+ type regions 11, 12 and P type regions 7, 9, 10 which define circuit components of the device. Isolation pocket 3 is wholly covered by a first metallisation 21 connect to ground. The metallisation 21 is in turn protected by a layer of insulating material 18 suitable for allowing the crossing of metal tracks or of a second metallisation for the connection of the different components.

75. 发明授权

US5141883A Process for the manufacture of power-MOS semiconductor devices 失效
标题翻译：功率MOS半导体器件的制造工艺
公开(公告)号：US5141883A
公开(公告)日：1992-08-25
申请号：US632485
申请日：1990-12-24
申请人： Giuseppe Ferla , Carmelo Magro , Paolo Lanza
发明人： Giuseppe Ferla , Carmelo Magro , Paolo Lanza
IPC分类号： H01L21/28 , H01L21/336 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/7802 , H01L29/456 , H01L29/4933 , Y10S148/126
摘要： A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.

76. 发明授权

US4881117A Semiconductor power device formed of a multiplicity of identical parallel-connected elements 失效
标题翻译：半导体功率器件由多个相同的并联元件形成
公开(公告)号：US4881117A
公开(公告)日：1989-11-14
申请号：US582793
申请日：1984-02-23
申请人： Luciano Gandolfi , Giuseppe Ferla
发明人： Luciano Gandolfi , Giuseppe Ferla
IPC分类号： H01L25/18 , H01L23/48 , H01L23/52 , H01L25/04 , H01L25/07
CPC分类号： H01L24/72 , H01L23/52 , H01L25/072 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/19043
摘要： A multiplicity of semiconductor chips constituting the active elements of a semiconductor power device are attached, in a predetermined configuration, to a metal plate which acts as both a support and a first electrical terminal. Two other electrical terminals are formed by two metal electrodes having an interdigitated structure with the fingers of one electrode being inserted between those of the other electrode and which are positioned above the semiconductor chips and have tabs for establishing a connection between the electrodes and the two contact areas of each chip.
摘要翻译：构成半导体功率器件的有源元件的多个半导体芯片以预定的配置被附接到充当支撑体和第一电气端子的金属板。另外两个电端子由具有交叉指状结构的两个金属电极形成，一个电极的指状物插在另一个电极的指状物之间，并且位于半导体芯片之上，并且具有用于在电极和两个触点之间建立连接的突片每个芯片的区域。

77. 发明授权

US4310571A Process for producing a calibrated resistance element 失效
标题翻译：用于制造校准电阻元件的工艺
公开(公告)号：US4310571A
公开(公告)日：1982-01-12
申请号：US34204
申请日：1979-04-27
申请人： Vincenzo Daniele , Giuseppe Corda , Andrea Ravaglia , Giuseppe Ferla
发明人： Vincenzo Daniele , Giuseppe Corda , Andrea Ravaglia , Giuseppe Ferla
IPC分类号： H01C17/24 , H01L21/02 , H01L21/033 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/10 , H01C17/06
CPC分类号： H01L28/20 , H01L21/033 , Y10T29/49082 , Y10T29/49099
摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.
摘要翻译：预定电阻率的丝状元素，例如通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对化学物质如能够侵蚀电介质层的氢氟酸。接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。

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