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    • 3. 发明申请
    • METHOD FOR MANUFACTURING A HIGH INTEGRATION DENSITY POWER MOS DEVICE
    • 用于制造高集成度密度功率MOS器件的方法
    • US20090321826A1
    • 2009-12-31
    • US12551999
    • 2009-09-01
    • Giuseppe ARENAGiuseppe FerlaMarco Camalleri
    • Giuseppe ARENAGiuseppe FerlaMarco Camalleri
    • H01L29/78
    • H01L29/7802H01L21/2815H01L29/42372H01L29/42376H01L29/4238H01L29/4933H01L29/66712
    • A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.
    • 用于实现高集成度功率MOS器件的方法包括以下步骤:提供具有第一类型导电性的掺杂半导体衬底; 在所述基板上形成具有较低导电率的半导体层; 在半导体层上形成厚度介于3000和13000A(埃)之间的介电层; 在电介质层上沉积硬掩模层; 通过掩模层掩蔽硬掩模层; 蚀刻硬掩模层和下面的介电层以限定多个硬掩模部分以保护所述介电层; 去除掩蔽层; 各向同性和横向蚀刻所述介电层,在所述硬掩模部分下面的所述介电层中形成横向空腔; 形成厚度为150至1500A(埃)的栅极氧化物,其在所述空腔中沉积导体材料并且在其上方,以形成与包括所述厚介电层和所述栅极氧化物的栅极结构完全对准的凹陷间隔物。
    • 7. 发明授权
    • Single feature size MOS technology power device
    • 单功能尺寸MOS技术电源设备
    • US06468866B2
    • 2002-10-22
    • US09427237
    • 1999-10-26
    • Ferruccio FrisinaAngelo MagriGiuseppe FerlaRichard A. Blanchard
    • Ferruccio FrisinaAngelo MagriGiuseppe FerlaRichard A. Blanchard
    • H01L21336
    • H01L29/7802H01L29/0696H01L29/0847H01L29/0869H01L29/1095H01L29/66333
    • A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.
    • MOS技术功率器件包括第一导电类型的半导体材料层,覆盖半导体材料层的导电绝缘栅极层和多个基本功能单元。 导电绝缘栅层包括置于半导体材料层上方的第一绝缘材料层,位于第一绝缘材料层上方的导电材料层和置于导电材料层上方的第二绝缘材料层。 每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。 每个基本功能单元还包括在细长体区域上方延伸的绝缘栅极层中的细长窗口。 每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区,插入有细长体区的一部分,其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括多个绝缘材料侧壁间隔物,其沿着每个细长窗口的细长边缘设置在半导体材料层之上,以密封绝缘栅极层中每个细长窗口的边缘与设置在绝缘栅极上的源极金属层 层和半导体材料层。 源极金属层沿着细长主体区域的长度通过每个细长窗口接触每个体区域和每个源极区域。
    • 10. 发明授权
    • Process of making a MOS-technology power device
    • 制造MOS技术电源设备的过程
    • US5817546A
    • 1998-10-06
    • US576989
    • 1995-12-19
    • Giuseppe FerlaFerruccio Frisina
    • Giuseppe FerlaFerruccio Frisina
    • H01L21/336H01L29/10H01L21/332
    • H01L29/66712H01L29/1095Y10S148/126
    • A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type. The process includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. A dopant of the second conductivity type is implanted twice at different concentrations and energies into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. A dopant of the first conductivity type is then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.
    • 一种工艺形成包括第一导电类型的半导体材料层和设置在其中的体区的MOS技术功率器件。 身体区域包括第二导电类型的重掺杂区域,第二导电类型的轻掺杂区域和第一导电类型的重掺杂区域。 该方法包括在半导体材料层的表面的部分上形成绝缘栅极层,以使半导体材料层的选定部分露出。 将第二导电类型的掺杂剂以不同的浓度和能量注入到半导体材料层的选定区域中两次。 注入的离子热扩散以形成体区,每个体区包括基本上与绝缘栅层的边缘对准的重掺杂区,以及通过第一掺杂剂在绝缘栅层下方的横向扩散形成的轻掺杂区。 然后将第一导电类型的掺杂剂注入到重掺杂区域中以形成与绝缘栅极层的边缘基本对准的源极区域。