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71. 发明申请

US20120074483A1 EEPROM CELL 有权
标题翻译： EEPROM单元
公开(公告)号：US20120074483A1
公开(公告)日：2012-03-29
申请号：US12888437
申请日：2010-09-23
申请人： Sung Mun JUNG , Kian Hong LIM , Jianbo YANG , Swee Tuck WOO , Sanford CHU
发明人： Sung Mun JUNG , Kian Hong LIM , Jianbo YANG , Swee Tuck WOO , Sanford CHU
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
摘要翻译：公开了一种形成装置的方法。该方法包括提供准备有单元区域的基板，并在单元区域中形成第一和第二晶体管的第一和第二栅极。第一栅极包括围绕第一子栅极的第二子栅极。第一栅极的第一和第二子栅极由第一栅极介电层分开。第二栅极包括围绕第一子栅极的第二子栅极。第二栅极的第一和第二子栅极由第二栅极间介电层分开。该方法还包括形成第一和第二晶体管的第一和第二结。第一栅极端子形成并耦合到第一晶体管的第二子栅极。第二栅极端子形成并耦合到至少第二晶体管的第一子栅极。

72. 发明申请

US20120007214A1 INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有分层电容器的集成电路系统及其制造方法
公开(公告)号：US20120007214A1
公开(公告)日：2012-01-12
申请号：US13236295
申请日：2011-09-19
申请人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
发明人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

73. 发明申请

US20110049625A1 ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION 有权
标题翻译：非对称晶体管器件及其制造方法
公开(公告)号：US20110049625A1
公开(公告)日：2011-03-03
申请号：US12550407
申请日：2009-08-31
申请人： Chung Foong TAN , Eng Huat TOH , Jae Gon LEE , Sanford CHU
发明人： Chung Foong TAN , Eng Huat TOH , Jae Gon LEE , Sanford CHU
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/66659 , H01L29/7848 , H01L29/78603 , H01L29/78618
摘要： Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.
摘要翻译：本发明的实施例提供一种包括半导体衬底，源极区，漏极区和沟道区的不对称晶体管器件。沟道区设置在源极和漏极区之间，源极，漏极和沟道区域设置在衬底中。该器件具有设置在源极区域下方且不在漏极区域下方的掩埋绝缘介质层，从而形成不对称结构。掩埋绝缘介质层设置成与源区域的下表面邻接。

74. 发明申请

US20100320529A1 INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有高压晶体管的集成电路系统及其制造方法
公开(公告)号：US20100320529A1
公开(公告)日：2010-12-23
申请号：US12488451
申请日：2009-06-19
申请人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
发明人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/1041 , H01L29/4238
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.
摘要翻译：一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。

75. 发明申请

US20100038752A1 MODULAR & SCALABLE INTRA-METAL CAPACITORS 审中-公开
标题翻译：模块化和可量程的金属电容器
公开(公告)号：US20100038752A1
公开(公告)日：2010-02-18
申请号：US12192131
申请日：2008-08-15
申请人： Chit Hwei NG , Chaw Sing HO , Kerwin KHU , Sanford CHU
发明人： Chit Hwei NG , Chaw Sing HO , Kerwin KHU , Sanford CHU
IPC分类号： H01L29/00 , H01G4/005 , H01L21/20
CPC分类号： H01L23/5223 , H01G4/005 , H01G4/01 , H01L27/0207 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell.
摘要翻译：金属间电容器单元包括形成在同一器件层中的第一电极和第二电极。电介质层分离电极。第一电极基本上被第二电极包围。第一和第二电极之间的对准不会实质上改变单位电池的电容。

76. 发明申请

US20090302385A1 HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER 有权
标题翻译：具有增强型电介质层的高性能LDMOS器件
公开(公告)号：US20090302385A1
公开(公告)日：2009-12-10
申请号：US12134860
申请日：2008-06-06
申请人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
发明人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7846
摘要： An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.
摘要翻译： LDMOS器件包括具有表面的衬底和覆盖该表面的栅电极，并且在栅电极下方的衬底中限定沟道区。漏极区域与沟道区域隔开隔离区域。隔离区域包括高拉伸应力的区域，并且被配置为在靠近漏极区域的基板中引起局部应力。隔离区域中的高拉伸应力的区域可以由高应力氧化硅或高应力氮化硅形成。在优选实施例中，隔离区是形成在栅极电极和漏极区域中间的衬底中的浅沟槽隔离区。

77. 发明申请

US20090146258A1 SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiCMOS PROCESS 有权
标题翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管
公开(公告)号：US20090146258A1
公开(公告)日：2009-06-11
申请号：US12368283
申请日：2009-02-09
申请人： Shaoqiang ZHANG , Purakh Raj VERMA , Sanford CHU
发明人： Shaoqiang ZHANG , Purakh Raj VERMA , Sanford CHU
IPC分类号： H01L29/72 , H01L21/8238 , H01L21/8249
CPC分类号： H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/7378
摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
摘要翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。作为插件模块，与SiGe BiCMOS工艺完全集成。高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。自对准N +基极植入可以减少基极电阻和寄生EB电容。极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

78. 发明申请

US20080191258A1 LOW VOLTAGE COEFFICIENT MOS CAPACITORS 审中-公开
标题翻译：低电压系数MOS电容
公开(公告)号：US20080191258A1
公开(公告)日：2008-08-14
申请号：US11672971
申请日：2007-02-09
申请人： Tan Li JIA , Sanford CHU , Michael CHENG
发明人： Tan Li JIA , Sanford CHU , Michael CHENG
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L29/94
摘要： A low voltage coefficient MOS capacitor includes first and second dielectric layers between first and second capacitor plates, with a common plate separating the dielectric layers. First and second terminals are coupled to first and second capacitor plates.
摘要翻译：低电压系数MOS电容器包括在第一和第二电容器板之间的第一和第二电介质层，其中共同的板分离电介质层。第一和第二端子耦合到第一和第二电容器板。

79. 发明授权

US07382027B2 MOSFET device with low gate contact resistance 有权
标题翻译：具有低栅极接触电阻的MOSFET器件
公开(公告)号：US07382027B2
公开(公告)日：2008-06-03
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

80. 发明申请

US20070134854A1 Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process 有权
标题翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管
公开(公告)号：US20070134854A1
公开(公告)日：2007-06-14
申请号：US11302479
申请日：2005-12-13
申请人： Shaoqiang Zhang , Purakh Verma , Sanford Chu
发明人： Shaoqiang Zhang , Purakh Verma , Sanford Chu
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/7378
摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
摘要翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。作为插件模块，与SiGe BiCMOS工艺完全集成。高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。自对准N +基极植入可以减少基极电阻和寄生EB电容。极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

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