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1. 发明授权

US08750037B2 Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof 有权
标题翻译：利用冲击电离和隧穿的非易失性存储器及其制造方法
公开(公告)号：US08750037B2
公开(公告)日：2014-06-10
申请号：US12456440
申请日：2009-06-16
申请人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
发明人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
IPC分类号： G11C16/04
CPC分类号： H01L29/7885 , G11C16/0408 , H01L29/42336 , H01L29/66825
摘要： A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.
摘要翻译：公开并构造了非易失性存储器件（和制造方法），以使得能够在器件的第一部分中使用电离冲击处理的写入操作以及在器件的第二部分中使用隧道工艺的读取操作。非易失性存储器件（1）增加了热载流子注入效率，（2）降低功耗，（3）使非易失性存储器件中的电压和器件缩放。

2. 发明申请

US20130175577A1 NFET Device with Tensile Stressed Channel Region and Methods of Forming Same 审中-公开
标题翻译：具有拉伸强度通道区域的NFET器件及其形成方法相同
公开(公告)号：US20130175577A1
公开(公告)日：2013-07-11
申请号：US13346299
申请日：2012-01-09
申请人： Chung Foong Tan , Maciej Wiatr , Stephan Kronholz
发明人： Chung Foong Tan , Maciej Wiatr , Stephan Kronholz
IPC分类号： H01L27/092 , H01L29/78 , H01L21/28
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/66651
摘要： Disclosed herein is an NFET device with a tensile stressed channel region and various methods of making such an NFET device. In one example, the NFET transistor includes a semiconducting substrate, a first layer of semiconductor material positioned above the substrate, a second capping layer of semiconductor material positioned above the first layer of semiconductor material and a gate electrode structure positioned above the second capping layer of semiconductor material.
摘要翻译：本文公开了具有拉伸应力通道区域的NFET器件和制造这种NFET器件的各种方法。在一个示例中，NFET晶体管包括半导体衬底，位于衬底上方的第一半导体材料层，位于第一半导体材料层上方的半导体材料的第二覆盖层和位于第二覆盖层上方的栅电极结构半导体材料。

3. 发明授权

US08470700B2 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
公开(公告)号：US08470700B2
公开(公告)日：2013-06-25
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L21/26
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

4. 发明申请

US20120292707A1 NANO-ELECTRO-MECHANICAL SYSTEM (NEMS) STRUCTURES ON BULK SUBSTRATES 有权
标题翻译：纳米电子机械系统（NEMS）结构在大块基板上
公开(公告)号：US20120292707A1
公开(公告)日：2012-11-22
申请号：US13108439
申请日：2011-05-16
申请人： Eng Huat Toh , Elgin Quek , Chung Foong Tan
发明人： Eng Huat Toh , Elgin Quek , Chung Foong Tan
IPC分类号： H01L21/336 , H01L29/78 , B82Y99/00
CPC分类号： H01L29/685 , B81B3/0081 , B81B2203/0109 , B81B2207/015 , B82Y10/00 , G11C11/56 , G11C23/00 , G11C2213/16 , H01L21/28282 , H01L21/764 , H01L27/1052 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L27/1104 , H01L27/11573 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap.
摘要翻译：半导体器件由体积衬底上的纳米机电系统（NEMS）逻辑或存储器形成。实施例包括直接在体基板上形成源极/漏极区域，形成连接源极/漏极区域的鳍片，形成两个栅极，鳍片的每一侧上一个，两个栅极与本体衬底绝缘，以及形成衬底栅极在散装衬底中。翅片与具有气隙的两个栅极和衬底栅极中的每一个分离。

5. 发明申请

US20120228705A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228705A1
公开(公告)日：2012-09-13
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

6. 发明申请

US20120228695A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228695A1
公开(公告)日：2012-09-13
申请号：US13046313
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层，分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成栅极堆叠彼此分离并具有不同的栅极电介质材料。

7. 发明申请

US20120139046A1 ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION 有权
标题翻译：非对称晶体管器件及其制造方法
公开(公告)号：US20120139046A1
公开(公告)日：2012-06-07
申请号：US13366355
申请日：2012-02-06
申请人： Chung Foong TAN , Eng Huat TOH , Jae Gon LEE , Sanford CHU
发明人： Chung Foong TAN , Eng Huat TOH , Jae Gon LEE , Sanford CHU
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/66659 , H01L29/7848 , H01L29/78603 , H01L29/78618
摘要： Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.
摘要翻译：本发明的实施例提供一种包括半导体衬底，源极区，漏极区和沟道区的不对称晶体管器件。沟道区设置在源极和漏极区之间，源极，漏极和沟道区域设置在衬底中。该器件具有设置在源极区域下方且不在漏极区域下方的掩埋绝缘介质层，从而形成不对称结构。掩埋绝缘介质层设置成与源区域的下表面邻接。

8. 发明申请

US20120119281A1 INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有带状材料的集成电路系统及其制造方法
公开(公告)号：US20120119281A1
公开(公告)日：2012-05-17
申请号：US12947530
申请日：2010-11-16
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.
摘要翻译：一种制造集成电路系统的方法包括：提供具有沟道区的衬底; 在所述沟道区的一部分上形成栅极堆叠，所述栅极堆叠具有用于存储电荷的浮动栅极; 在所述衬底中邻近所述栅极堆叠形成源极凹槽; 以及通过在源凹槽中层叠第一带隙材料来形成源。

9. 发明申请

US20100315884A1 Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof 有权
标题翻译：利用冲击电离和隧穿的非易失性存储器及其制造方法
公开(公告)号：US20100315884A1
公开(公告)日：2010-12-16
申请号：US12456440
申请日：2009-06-16
申请人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
发明人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
IPC分类号： G11C16/04 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7885 , G11C16/0408 , H01L29/42336 , H01L29/66825
摘要： A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.
摘要翻译：公开并构造了非易失性存储器件（和制造方法），以使得能够在器件的第一部分中使用电离冲击处理的写入操作以及在器件的第二部分中使用隧道工艺的读取操作。非易失性存储器件（1）增加了热载流子注入效率，（2）降低功耗，（3）使非易失性存储器件中的电压和器件缩放。

10. 发明申请

US20090246920A1 METHODS FOR NORMALIZING STRAIN IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中正常化应变的方法
公开(公告)号：US20090246920A1
公开(公告)日：2009-10-01
申请号：US12057072
申请日：2008-03-27
申请人： Lee Wee Teo , Chung Foong Tan , Alain Chan , Elgin Kiok Boone Quek
发明人： Lee Wee Teo , Chung Foong Tan , Alain Chan , Elgin Kiok Boone Quek
IPC分类号： H01L21/8232
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.
摘要翻译：通过根据器件的种群密度选择性地将应变诱导结构与半导体器件的受影响区域分离开，使得在半导体器件中诱导应变的电性能增强效应通过具有变化的器件部件的种群密度的衬底基本上均匀组件。通过在诸如MOS晶体管栅电极的器件部件上选择性地形成侧壁间隔而获得不同的间隔距离，其中侧壁间隔物在具有相对较高密度的器件部件的区域中具有相对较小的宽度，并且具有相对低密度的器件组件。通过改变应变诱导结构与受影响部件的分离距离，在集成电路中的器件的各种部件中获得均匀的电性能，而不管部件群体密度如何。

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