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1. 发明授权

US06861317B1 Method of making direct contact on gate by using dielectric stop layer 失效
标题翻译：通过使用介电阻挡层在栅极上直接接触的方法
公开(公告)号：US06861317B1
公开(公告)日：2005-03-01
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（fmax）和减小的栅极延迟。

2. 发明授权

US07382027B2 MOSFET device with low gate contact resistance 有权
标题翻译：具有低栅极接触电阻的MOSFET器件
公开(公告)号：US07382027B2
公开(公告)日：2008-06-03
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

3. 发明授权

US06972237B2 Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth 有权
公开(公告)号：US06972237B2
公开(公告)日：2005-12-06
申请号：US10725670
申请日：2003-12-01
申请人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jia Zhen Zheng , Jian Xun Li
发明人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jia Zhen Zheng , Jian Xun Li
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

4. 发明授权

US07238971B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US07238971B2
公开(公告)日：2007-07-03
申请号：US11123748
申请日：2005-05-04
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L29/732
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

5. 发明授权

US07049201B2 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US07049201B2
公开(公告)日：2006-05-23
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
发明人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

6. 发明授权

US06924202B2 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact 有权
标题翻译：具有自对准发射极和侧壁基极接触的异质结双极晶体管
公开(公告)号：US06924202B2
公开(公告)日：2005-08-02
申请号：US10683142
申请日：2003-10-09
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。在基底沟槽中形成具有侧壁部分和底部的本征基底结构。在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。在基极接触层和发射极结构之上形成层间电介质层。通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

7. 发明授权

US06908824B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US06908824B2
公开(公告)日：2005-06-21
申请号：US10703284
申请日：2003-11-06
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

8. 发明授权

US06835631B1 Method to enhance inductor Q factor by forming air gaps below inductors 有权
标题翻译：通过在电感器下方形成气隙来增强电感Q因子的方法
公开(公告)号：US06835631B1
公开(公告)日：2004-12-28
申请号：US10718193
申请日：2003-11-20
申请人： Zheng Jia Zhen , Sanford Chu , Ng Chit Hwei , Lap Chan , Purakh Raj Verma
发明人： Zheng Jia Zhen , Sanford Chu , Ng Chit Hwei , Lap Chan , Purakh Raj Verma
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01L23/5222 , H01L23/5227 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.
摘要翻译：一种提高电感器性能的方法，包括以下步骤。提供一种其上形成有第一氧化物层的结构。在第一氧化物层上形成较低的低k电介质层。在下部低k电介质层上形成第二氧化物层。图案化第二氧化物层以通过暴露下部低k电介质层的一部分而在其中形成至少一个孔。通过下部低k介电层的暴露部分蚀刻到下部低k电介质层中，从而蚀刻下蚀刻的低k介电层内的至少一个相应的气隙。在图案化的第二氧化物层上形成上部低k电介质层。至少一个电感器形成在上部低k电介质层内并在至少一个气隙上形成，从而提高了电感器的性能。

9. 发明授权

US06638844B1 Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill 有权
标题翻译：通过背面沟槽和填充来减少半导体技术中射频CMOS（RFCMOS）器件的衬底耦合/噪声的方法
公开(公告)号：US06638844B1
公开(公告)日：2003-10-28
申请号：US10207549
申请日：2002-07-29
申请人： Purakh Raj Verma , Sanford Chu , Chit Hwei , Lap Chan
发明人： Purakh Raj Verma , Sanford Chu , Chit Hwei , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L27/08 , H01L21/76224 , H01L21/823878 , H01L27/0617
摘要： A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.
摘要翻译：一种降低一个或多个RFCMOS组件的衬底耦合和噪声的方法，包括以下步骤。提供具有前侧和背侧的基板。在衬底上形成一个或多个RFCMOS部件。一个或多个隔离结构在靠近一个或多个RFCOMS组件的衬底内形成。蚀刻衬底的背面以在衬底内并且在至少一个或多个隔离结构上形成相应的沟槽。相应的沟槽被电介质材料填充，由此降低了一个或多个RFCMOS部件的衬底耦合和噪声。

10. 发明授权

US07022578B2 Heterojunction bipolar transistor using reverse emitter window 有权
标题翻译：使用反向发射极窗口的异质结双极晶体管
公开(公告)号：US07022578B2
公开(公告)日：2006-04-04
申请号：US10683713
申请日：2003-10-09
申请人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jian Xun Li , Zhen Jia Zheng
发明人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jian Xun Li , Zhen Jia Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/41708 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，集电极区域上的化合物半导体材料的本征基极区域，非本征基极区域，发射极结构，层间电介质层集电极区域，非本征基极区域和发射极结构以及通过层间介质层到基极区域，发射极结构和集电极区域的连接。通过在本征基极区域上形成反向发射极窗口形成发射极结构，其随后被蚀刻以形成其中具有多层反向绝缘间隔物的发射极窗口。

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