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1. 发明授权

US08138051B2 Integrated circuit system with high voltage transistor and method of manufacture thereof 有权
标题翻译：具有高压晶体管的集成电路系统及其制造方法
公开(公告)号：US08138051B2
公开(公告)日：2012-03-20
申请号：US12488451
申请日：2009-06-19
申请人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
发明人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
IPC分类号： H01L21/336 , H01L29/94 , H01L29/76 , H01L31/119 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/1041 , H01L29/4238
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.
摘要翻译：一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。

2. 发明申请

US20100320529A1 INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有高压晶体管的集成电路系统及其制造方法
公开(公告)号：US20100320529A1
公开(公告)日：2010-12-23
申请号：US12488451
申请日：2009-06-19
申请人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
发明人： Yemin Dong , Purakh Raj Verma , Xin Zou , Chao Cheng , Shao-fu Sanford Chu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/1041 , H01L29/4238
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.
摘要翻译：一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。

3. 发明授权

US08340915B2 Systems and methods for analyzing microarrays 有权
标题翻译：用于分析微阵列的系统和方法
公开(公告)号：US08340915B2
公开(公告)日：2012-12-25
申请号：US11866964
申请日：2007-10-03
申请人： Lei M. Li , Chao Cheng , Huanying Ge
发明人： Lei M. Li , Chao Cheng , Huanying Ge
IPC分类号： G01N33/50 , G01N33/48
CPC分类号： G06F19/20
摘要： The present invention discloses methods and systems for analyzing microarray data. The method includes the general steps of providing microarray data, normalizing the data using a least trimmed squares regression, and then analyzing the normalized microarray data to obtain a desired result such as an expression profile. There is also disclosed a method of subdividing an array into subarrays before normalization. This approach provides a method for improving measurement accuracy and salvaging array data from arrays containing minor defects. Also disclosed is a Probe-Treatment-Reference (PTR) model for streamlining normalization and summarization of microarray data by allowing multiple references. Other aspects of the present invention include computer systems and computer readable media encoding methods of the present invention.
摘要翻译：本发明公开了用于分析微阵列数据的方法和系统。该方法包括提供微阵列数据的一般步骤，使用最小修正平方回归归一化数据，然后分析归一化微阵列数据以获得期望的结果，例如表达谱。还公开了在归一化之前将阵列细分为子阵列的方法。这种方法提供了一种提高测量精度并从包含轻微缺陷的阵列中挽救阵列数据的方法。还公开了一种用于通过允许多个参考来精简归一化和汇总微阵列数据的探针治疗 - 参考（PTR）模型。本发明的其它方面包括本发明的计算机系统和计算机可读介质编码方法。

4. 发明申请

US20080319679A1 SYSTEMS AND METHODS FOR ANALYZING MICROARRAYS 有权
标题翻译：用于分析微阵列的系统和方法
公开(公告)号：US20080319679A1
公开(公告)日：2008-12-25
申请号：US11866964
申请日：2007-10-03
申请人： Lei M. Li , Chao Cheng , Huanying Ge
发明人： Lei M. Li , Chao Cheng , Huanying Ge
IPC分类号： G06F17/18 , G01N33/48
CPC分类号： G06F19/20
摘要： The present invention discloses methods and systems for analyzing microarray data. The method includes the general steps of providing microarray data, normalizing the data using a least trimmed squares regression, and then analyzing the normalized microarray data to obtain a desired result such as an expression profile. There is also disclosed a method of subdividing an array into subarrays before normalization. This approach provides a method for improving measurement accuracy and salvaging array data from arrays containing minor defects. Also disclosed is a Probe-Treatment-Reference (PTR) model for streamlining normalization and summarization of microarray data by allowing multiple references. Other aspects of the present invention include computer systems and computer readable media encoding methods of the present invention.
摘要翻译：本发明公开了用于分析微阵列数据的方法和系统。该方法包括提供微阵列数据的一般步骤，使用最小修正平方回归归一化数据，然后分析归一化微阵列数据以获得期望的结果，例如表达谱。还公开了在归一化之前将阵列细分为子阵列的方法。这种方法提供了一种提高测量精度并从包含轻微缺陷的阵列中挽救阵列数据的方法。还公开了一种用于通过允许多个参考来精简归一化和汇总微阵列数据的探针治疗 - 参考（PTR）模型。本发明的其它方面包括本发明的计算机系统和计算机可读介质编码方法。

5. 发明申请

US20080109709A1 Hardware-Efficient, Low-Latency Architectures for High Throughput Viterbi Decoders 审中-公开
标题翻译：用于高吞吐量维特比解码器的硬件高效，低延迟架构
公开(公告)号：US20080109709A1
公开(公告)日：2008-05-08
申请号：US11951822
申请日：2007-12-06
申请人： Chao Cheng , Keshab Parhi
发明人： Chao Cheng , Keshab Parhi
IPC分类号： H03M13/27 , G06F11/10
CPC分类号： H03M13/4107 , H03M13/395 , H03M13/3961
摘要： A low-latency, high-throughput rate Viterbi decoder implemented in a K1-nested layered look-ahead (LLA) manner, combines K1-trellis steps, with look-ahead step M, where K
摘要翻译：以K1嵌套分层预先（LLA）方式实现的低等待时间，高吞吐率维特比解码器将K1-网格步骤与先行步骤M组合，其中K

6. 外观设计

USD579231S1 Fold-n-stow file cabinet 有权
标题翻译：折叠式文件柜
公开(公告)号：USD579231S1
公开(公告)日：2008-10-28
申请号：US29290649
申请日：2007-12-31
申请人： Chao Cheng
设计人： Chao Cheng

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