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61. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

62. 发明授权

US5276648A Testing method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试方法
公开(公告)号：US5276648A
公开(公告)日：1994-01-04
申请号：US818274
申请日：1992-01-08
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

63. 发明授权

US5258644A Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5258644A
公开(公告)日：1993-11-02
申请号：US918133
申请日：1992-07-23
申请人： Akihiro Tamba , Yutaka Kobayashi , Tetsurou Matsumoto
发明人： Akihiro Tamba , Yutaka Kobayashi , Tetsurou Matsumoto
IPC分类号： H01L29/735 , H01L29/00
CPC分类号： H01L29/735
摘要： An improved bipolar transistor is provided which can be formed using a number of process steps which are similar to those used for forming MOSFETs. As such, the bipolar transistor is particularly useful in BiCMOS device arrangements. In accordance with one embodiment, a bipolar transistor is formed so that at least one of the emitter and collector regions has a high impurity region and a low impurity region. The collector and emitter regions of the device are formed in the base region to be spaced apart from one another, and the base electrode is arranged to cover the area of the base region between them. In an alternative embodiment, two collector regions can be provided in a base region on opposite sides of an emitter which is also formed in the base region. Two base electrodes can then be respectively provided in the areas between the two collectors and the emitter region. The bipolar transistors are particularly useful for forming a horizontal bipolar transistor structure. Because the bipolar transistors can be formed using the same types of steps used in the manufacture of MOSFETs, the manufacturing costs of the device can be reduced without sacrificing operational capabilities. This is particularly true in the manufacture of BiCMOS devices because many simultaneous manufacturing steps can be used for manufacturing the bipolar transistors and the MOSFETs.
摘要翻译：提供了一种改进的双极晶体管，其可以使用与用于形成MOSFET的那些类似的多个工艺步骤形成。因此，双极晶体管在BiCMOS器件布置中特别有用。根据一个实施例，形成双极晶体管，使得发射极和集电极区域中的至少一个具有高杂质区域和低杂质区域。器件的集电极和发射极区域形成在基极区域中以彼此间隔开，并且基极布置成覆盖它们之间的基极区域的区域。在替代实施例中，两个集电极区域可以设置在也形成在基极区域中的发射极的相对侧上的基极区域中。然后可以在两个集电极和发射极区域之间的区域中分别提供两个基极。双极晶体管特别适用于形成水平双极晶体管结构。因为可以使用与制造MOSFET相同类型的步骤来形成双极晶体管，所以可以降低器件的制造成本而不牺牲操作能力。在BiCMOS器件的制造中尤其如此，因为许多同时的制造步骤可用于制造双极晶体管和MOSFET。

64. 发明授权

US5150325A Bi-CMOS semiconductor memory device, including improved layout structure and testing method 失效
标题翻译： Bi-CMOS半导体存储器件，包括改进的布局结构和测试方法
公开(公告)号：US5150325A
公开(公告)日：1992-09-22
申请号：US496227
申请日：1990-03-20
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读信号作为固化信号传输，然后转换为电压信号以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

65. 外观设计

USD328259S Pedometer 失效
公开(公告)号：USD328259S
公开(公告)日：1992-07-28
申请号：US520219
申请日：1990-05-04
申请人： Yutaka Kobayashi
设计人： Yutaka Kobayashi

66. 发明授权

US4962052A Method for producing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US4962052A
公开(公告)日：1990-10-09
申请号：US478050
申请日：1990-02-07
申请人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
发明人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/10 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L27/105
摘要： A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.
摘要翻译：公开了一种在其外围电路中具有LDD结构的MISFET和垂直型双极晶体管的存储器LSI的制造方法。更具体地，用于形成LDD结构的所述MISFET的低杂质浓度区域的杂质被侧向引入双极晶体管的发射极 - 基极结。通过引入所述杂质，降低了基极表面附近的有效杂质浓度，提高了双极晶体管的截止频率。

67. 发明授权

US4693758A Method of making devices in silicon, on insulator regrown by laser beam 失效
标题翻译：在硅中制造器件的方法，在绝缘体上由激光束重新生长
公开(公告)号：US4693758A
公开(公告)日：1987-09-15
申请号：US784033
申请日：1985-10-04
申请人： Yutaka Kobayashi , Takaya Suzuki
发明人： Yutaka Kobayashi , Takaya Suzuki
IPC分类号： H01L29/78 , H01L21/20 , H01L21/205 , H01L21/26 , H01L21/268 , H01L21/428 , H01L21/86 , H01L27/12 , H01L29/786 , H01L21/263 , H01L21/225
CPC分类号： H01L27/12 , H01L21/0242 , H01L21/02433 , H01L21/0245 , H01L21/02516 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02686 , H01L21/268 , H01L29/78657 , Y10S117/904 , Y10S438/967
摘要： This invention relates to improvements in the SOS technology including the so-called laser annealing processing. According to this invention, a semiconductor layer of an SOS structure consists of the three layers of an interface layer made up of twins, a seed crystalline layer and a re-grown layer far thicker than the preceding two layers when viewed from the side of an insulating substrate. The re-grown layer is formed in such a way that a semiconductor layer deposited on the insulating substrate is irradiated with an electromagnetic wave, for example, pulsed ruby laser beam, which is absorbed substantially uniformly by a portion except the interface layer and the seed crystalline layer. According to this invention, the quality of the re-grown layer is improved, and the mobility of carriers is enhanced. As a result, the operating speed of a semiconductor device employing the SOS structure is raised, and the leakage current is reduced.
摘要翻译：本发明涉及SOS技术的改进，包括所谓的激光退火处理。根据本发明，SOS结构的半导体层由三层由双胞胎组成的界面层，晶种层和再生长层组成，当从绝缘基板。再生长层以这样的方式形成，使得沉积在绝缘基板上的半导体层被电磁波照射，例如脉冲红宝石激光束，其被除了界面层和种子之外的部分基本均匀地吸收晶体层。根据本发明，再生层的质量得到改善，并且载体的迁移率增强。结果，使用SOS结构的半导体器件的工作速度提高，并且泄漏电流降低。

68. 发明授权

US4657519A Plastic toy and method of manufacturing same 失效
标题翻译：塑料玩具及其制造方法
公开(公告)号：US4657519A
公开(公告)日：1987-04-14
申请号：US772884
申请日：1985-09-05
申请人： Yutaka Kobayashi
发明人： Yutaka Kobayashi
IPC分类号： A63H3/16 , A63H3/36 , A63H3/38 , A63H3/46 , A63H3/48 , A63H9/00
CPC分类号： A63H9/00 , A63H3/36 , A63H3/46
摘要： In manufacturing a toy doll conventionally, for instance, a front half constituting one half of a doll body, a rear half constituting the other half of a doll body and a set of head, hands and legs connected by a molding gate are molded separately. Thereafter, the head, hands and legs are separated from the gate one by one; the separated parts are independently arranged between the two halves one by one before fixing the two halves with the parts sandwiched therebetween. To improve the productivity, the various parts are molded, in connection with plural molding gates, at such positions that these parts are appropriately supported by and/or engageable with the front and rear halves. Therefore, it is possible to assemble the plastic toy doll immediately without separating various parts one by one from the gate before assembling the toy doll. The molding gates may be broken, after assembling, by twisting the hands or legs.
摘要翻译：在制造玩具娃娃时，例如，构成玩偶主体的一半的前半部分，构成玩偶主体的另一半的后半部分和通过模制门连接的一组头部，手和腿分别模制。此后，头，手，脚逐一与门口分开; 分离的部件在将两个部分夹在其间的部分固定之前，一个接一个地独立地设置在两个半部之间。为了提高生产率，各种部件在与多个模制浇口相关联的这些位置处被模制，这些部件被前半部和后半部适当地支撑和/或与其接合。因此，可以在组装玩具娃娃之前立即组装塑料玩具娃娃，而不必将各种零件从门上逐个分离。模制门可以在组装之后通过扭转手或腿而被破坏。

69. 发明授权

US08887268B2 Electronic device, password control method, and program 有权
标题翻译：电子设备，密码控制方法和程序
公开(公告)号：US08887268B2
公开(公告)日：2014-11-11
申请号：US12675255
申请日：2007-09-05
申请人： Osamu Uchida , Kazuya Fujimura , Yutaka Kobayashi
发明人： Osamu Uchida , Kazuya Fujimura , Yutaka Kobayashi
IPC分类号： H04L29/06 , G06F21/79
CPC分类号： G06F21/79
摘要： There is provided an electronic device capable of safely obtaining password information even when a password of an external storage device of any type is forgotten. An electronic device 100 includes an external memory card connection unit 108 connecting a memory card 200 capable of being locked by a card password, a password retention unit 101 retaining the password information including the card password, a device password retention unit 112 retaining a device password of the electronic device 100, an input unit 102 for inputting data, a device setting cancellation unit 111 determining whether or not the device password inputted by the input unit 102 and the device password retained in the device password retention unit 112 match with each other, and a control unit 109 outputting the password information or changing the card password of the external storage device set in the external storage device when the device passwords match with each other as a result of the determination.
摘要翻译：提供了即使当忘记了任何类型的外部存储装置的密码时能够安全地获得密码信息的电子装置。电子设备100包括连接能够被卡密码锁定的存储卡200的外部存储卡连接单元108，保存包括卡密码的密码信息的密码保持单元101，保存设备密码的设备密码保留单元112 电子设备100的输入单元102，用于输入数据的输入单元102，确定输入单元102输入的设备密码和设备密码保留单元112中保存的设备密码是否匹配的设备设置取消单元111，以及控制单元109，作为确定的结果，当设备密码彼此匹配时，输出密码信息或改变设置在外部存储设备中的外部存储设备的卡密码。

70. 发明授权

US08779325B2 Laser beam processing machine 有权
标题翻译：激光束加工机
公开(公告)号：US08779325B2
公开(公告)日：2014-07-15
申请号：US12073271
申请日：2008-03-03
申请人： Keiji Nomaru , Yutaka Kobayashi , Hiroshi Morikazu
发明人： Keiji Nomaru , Yutaka Kobayashi , Hiroshi Morikazu
IPC分类号： B23K26/02 , B23K26/00
CPC分类号： B23K26/355 , B23K26/032 , B23K26/034 , B23K26/04 , B23K26/06 , B23K26/0853 , B23K26/0869 , B23K26/40 , B23K2101/40 , B23K2103/50
摘要： A laser beam processing machine includes a laser beam application device and a controller. The controller controls deflecting of the optical axis of a pulse laser beam from the laser beam application device in the processing-feed direction according to a plurality of processing position coordinates, and according to the frequency of the beam, to ensure that there is a predetermined time interval between pulses applied to the same processing position coordinates. One pulse is applied at a time to each of the plurality of processing position coordinates.
摘要翻译：激光束处理机包括激光束施加装置和控制器。控制器根据多个处理位置坐标以及根据光束的频率来控制来自激光束施加装置的激光束施加装置的脉冲激光束的光轴的偏转，以确保存在预定的施加到相同处理位置坐标的脉冲之间的时间间隔。一次施加一个脉冲到多个处理位置坐标中的每一个。

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