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1. 发明专利

JP2005137402A Table for armchair 审中-公开
标题翻译： ARMCHAIR表
公开(公告)号：JP2005137402A
公开(公告)日：2005-06-02
申请号：JP2003373971
申请日：2003-11-04
申请人： Kazuo Mihashi , 三橋和雄
发明人： MIHASHI KAZUO
IPC分类号： A61G5/00
摘要： PROBLEM TO BE SOLVED: To provide a table capable of easily being attached to and detached from an armrest of an armchair and widely located in front of the armrest at the time of attaching and not coming off and not giving physically compressed feeling and being used for general purpose at ease for a long period of time.
SOLUTION: The table has arm portions 2a, 2b supporting the table portion 1 and simultaneously having fitting recessed portions formed for attaching to the armchair, and is attached to the armchair by simultaneously bringing the two inner faces facing each other of the recessed portion into contact with the upper face and lower face of the armchair so as to sandwiching the armchair, has portions coming into contact with the front end of the armrest and portions coming into contact with the rear end of the armrest, the movement in a longitudinal direction is inhibited by the contact of these portions. Further, the table has portions coming into contact with the side faces of the left and right arm pipe securing the above armrest, right and left movement is suppressed by the contact of the same. Attaching and detaching operations include only simply horizontally moving the arm portions 2a, 2b along the armrest.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够容易地附接到扶手椅的扶手上并且在安装时广泛位于扶手前方并且不会脱落并且不产生物理压缩感觉的桌子，长时间用于通用目的。解决方案：桌子具有支撑台部1的臂部2a，2b，同时具有形成为用于附接到扶手椅的嵌合凹部，并且通过同时使两个内表面彼此面对的凹陷部部分与扶手椅的上表面和下表面接触以夹住扶手椅，具有与扶手的前端接触的部分和与扶手的后端接触的部分，纵向的运动方向被这些部分的接触所阻止。此外，桌子具有与固定上述扶手的左右臂管的侧面接触的部分，左右移动通过与其接触来抑制。安装和拆卸操作仅仅是简单地沿着扶手水平地移动臂部分2a，2b。版权所有（C）2005，JPO＆NCIPI

2. 发明授权

US5276648A Testing method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试方法
公开(公告)号：US5276648A
公开(公告)日：1994-01-04
申请号：US818274
申请日：1992-01-08
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

3. 发明授权

US5150325A Bi-CMOS semiconductor memory device, including improved layout structure and testing method 失效
标题翻译： Bi-CMOS半导体存储器件，包括改进的布局结构和测试方法
公开(公告)号：US5150325A
公开(公告)日：1992-09-22
申请号：US496227
申请日：1990-03-20
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读信号作为固化信号传输，然后转换为电压信号以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

4. 发明授权

US5506804A Dynamic Random Access Type Semiconductor Device 失效
标题翻译：动态随机存取型半导体器件
公开(公告)号：US5506804A
公开(公告)日：1996-04-09
申请号：US159205
申请日：1993-11-30
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

5. 发明授权

US4941128A Semiconductor memory device having means for providing a precharge voltage equivalent to a prescribed selection voltage 失效
标题翻译：半导体存储器件具有用于提供等于规定选择电压的预充电电压的装置
公开(公告)号：US4941128A
公开(公告)日：1990-07-10
申请号：US185497
申请日：1988-04-25
申请人： Shouji Wada , Nobuo Komatsu , Mitsuhiro Takano , Sinichi Miyatake , Kazuo Mihashi , Hiromi Tsukada
发明人： Shouji Wada , Nobuo Komatsu , Mitsuhiro Takano , Sinichi Miyatake , Kazuo Mihashi , Hiromi Tsukada
IPC分类号： G11C11/4094
CPC分类号： G11C11/4094
摘要： A dynamic type RAM is provided wherein the level of a precharge control signal supplied to a gate of a precharge MOSFET to precharge complementary data lines to a half level is made the half level during a period from the memory access until the selection of the word line, at the latest. Also, the precharge control signal, corresponding to a memory mat selected according to establishing of an address, is set to a low level, while the precharge control signal corresponding to a non-selective memory mat is set to a high level.
摘要翻译：提供一种动态型RAM，其中提供给预充电MOSFET的栅极的预充电控制信号的电平在补充数据线预充电到一半电平时在从存储器访问到字线的选择期间成为半电平，最近。此外，对应于根据建立地址选择的存储器垫的预充电控制信号被设置为低电平，而对应于非选择性存储器垫的预充电控制信号被设置为高电平。

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