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1. 发明授权

US5276648A Testing method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试方法
公开(公告)号：US5276648A
公开(公告)日：1994-01-04
申请号：US818274
申请日：1992-01-08
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

2. 发明授权

US5150325A Bi-CMOS semiconductor memory device, including improved layout structure and testing method 失效
标题翻译： Bi-CMOS半导体存储器件，包括改进的布局结构和测试方法
公开(公告)号：US5150325A
公开(公告)日：1992-09-22
申请号：US496227
申请日：1990-03-20
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读信号作为固化信号传输，然后转换为电压信号以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

3. 发明授权

US5506804A Dynamic Random Access Type Semiconductor Device 失效
标题翻译：动态随机存取型半导体器件
公开(公告)号：US5506804A
公开(公告)日：1996-04-09
申请号：US159205
申请日：1993-11-30
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

4. 发明授权

US06226212B1 Semiconductor memory device, nonvolatile semiconductor memory device, and their data reading method 失效
标题翻译：半导体存储器件，非易失性半导体存储器件及其数据读取方法
公开(公告)号：US06226212B1
公开(公告)日：2001-05-01
申请号：US09050885
申请日：1998-03-31
申请人： Yoshinori Sakamoto , Tatsuya Ishii , Atsushi Nozoe , Hitoshi Miwa , Kazuyoshi Oshima
发明人： Yoshinori Sakamoto , Tatsuya Ishii , Atsushi Nozoe , Hitoshi Miwa , Kazuyoshi Oshima
IPC分类号： G11C702
CPC分类号： G11C16/28 , G11C7/06 , G11C7/065 , G11C11/5621 , G11C11/5642 , G11C16/0416 , G11C29/00
摘要： In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data reading time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.
摘要翻译：为了通过防止数据读取时通过数据线中的寄生电容发送到其他数据线的噪声来消除数据的错误读取，开关（Qt1和Qt1'）插入在用于放大数据线（DL）和数据线的电位，并且在数据线的电位被传送到读出放大器之后，感测放大器被馈送工作电压，并且开关被关断。

5. 发明授权

US06243313B1 Semiconductor memory device, nonvolatile semiconductor memory device, and their data reading method 有权
标题翻译：半导体存储器件，非易失性半导体存储器件及其数据读取方法
公开(公告)号：US06243313B1
公开(公告)日：2001-06-05
申请号：US09618940
申请日：2000-07-18
申请人： Yoshinori Sakamoto , Tatsuya Ishii , Atsushi Nozoe , Hitoshi Miwa , Kazuyoshi Oshima
发明人： Yoshinori Sakamoto , Tatsuya Ishii , Atsushi Nozoe , Hitoshi Miwa , Kazuyoshi Oshima
IPC分类号： G11C702
CPC分类号： G11C16/28 , G11C7/06 , G11C7/065 , G11C11/5621 , G11C11/5642 , G11C16/0416 , G11C29/00
摘要： In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data read time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.
摘要翻译：为了通过防止数据读取时通过数据线中的寄生电容发送到其他数据线的噪声来消除数据的错误读取，开关（Qt1和Qt1'）被插入在用于放大数据线（DL）和数据线的电位，并且在数据线的电位被传送到读出放大器之后，感测放大器被馈送工作电压，并且开关被关断。

6. 发明授权

US5304868A Non-inverting buffer circuit device and semiconductor memory circuit device 失效
标题翻译：同相缓冲电路器件和半导体存储器电路器件
公开(公告)号：US5304868A
公开(公告)日：1994-04-19
申请号：US783781
申请日：1991-10-29
申请人： Yuji Yokoyama , Kazuyuki Miyazawa , Hitoshi Miwa , Shoji Wada
发明人： Yuji Yokoyama , Kazuyuki Miyazawa , Hitoshi Miwa , Shoji Wada
IPC分类号： G11C11/409 , G11C7/10 , G11C8/06 , G11C11/417 , H03K19/013 , H03K19/0175 , H03K19/0944 , H03K19/02 , G11C8/00
CPC分类号： H03K19/0136 , G11C7/1051 , G11C8/06 , H03K19/09448
摘要： A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.
摘要翻译：提供了适用于半导体存储器的输入缓冲电路的非反相缓冲电路装置，可以减少逻辑门级的数量，实现高速运算。该电路被设计成使得输入级的MOS晶体管在输出级驱动双极晶体管以产生输出。并联连接在双极型晶体管的基极和集电极之间的n沟道MOS晶体管和p沟道MOS晶体管分别通过输入数字信号的反相信号和非反相信号进行开/关控制。在另一方面，输入缓冲电路包括反相信号输出电路和非反相信号输出电路，在设定模式下输入处于非反相状态的输入信号，并以复位模式输出处于规定电位的信号。反相信号输出电路包括产生其集电极电位的输出信号的双极晶体管，用于控制向双极晶体管供给集电极电流的第一开关电路，并联在基极和集电极之间的n沟道MOS晶体管用于根据输入信号向双极晶体管提供基极电流;以及第二开关电路，用于控制对双极晶体管的基极电流的供应，其中第一开关电路和第二开关电路选择性地开关控制。

7. 发明授权

US08709871B2 Stacked type semiconductor memory device and chip selection circuit 失效
标题翻译：堆叠型半导体存储器件和芯片选择电路
公开(公告)号：US08709871B2
公开(公告)日：2014-04-29
申请号：US13293897
申请日：2011-11-10
申请人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C2029/4402 , H01L2224/16145 , H01L2225/06513 , H01L2924/01021 , H01L2924/15311
摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
摘要翻译：通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括：多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

8. 发明申请

US20130201760A1 Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory 有权
标题翻译：在3D非易失性存储器中减少弱擦除类型读取干扰
公开(公告)号：US20130201760A1
公开(公告)日：2013-08-08
申请号：US13364518
申请日：2012-02-02
申请人： Yingda Dong , Man L. Mui , Hitoshi Miwa
发明人： Yingda Dong , Man L. Mui , Hitoshi Miwa
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.
摘要翻译：用于3D堆叠存储器件的读取处理为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及未选择的内存设备级别（Vcg_unsel）。通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。然后通过升高Vsgd_unsel和/或Vsgs_unsel使漏极侧和/或源极侧选择栅极变得不导通，从而中断升压。此外，当Vcg_unsel仍在增加时，通过使漏极侧和/或源极选择栅极再次导通，可以发生升压。或者，通道可以在Vbl驱动。两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。

9. 发明申请

US20070132085A1 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US20070132085A1
公开(公告)日：2007-06-14
申请号：US11635500
申请日：2006-12-08
申请人： Kayoko Shibata , Hiroaki Ikeda , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Kayoko Shibata , Hiroaki Ikeda , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/70 , H01L21/485 , H01L23/481 , H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.
摘要翻译：作为有缺陷的接触恢复元件，堆叠半导体器件包括其中信号路径被复用的并行布置系统，以及可操作以将信号路径切换到辅助信号路径的缺陷接触恢复电路。在串行数据传输的情况下，使用并行布置系统，并且需要非常高速的操作。在由于并行数据传送而导致信号数量大的情况下使用有缺陷接触恢复电路。

10. 发明申请

US20070126105A1 Stacked type semiconductor memory device and chip selection circuit 失效
标题翻译：堆叠型半导体存储器件和芯片选择电路
公开(公告)号：US20070126105A1
公开(公告)日：2007-06-07
申请号：US11634144
申请日：2006-12-06
申请人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C2029/4402 , H01L2224/16145 , H01L2225/06513 , H01L2924/01021 , H01L2924/15311
摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
摘要翻译：通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括：多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

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