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61. 发明授权

US08691647B1 Memory devices containing a high-K dielectric layer 有权
标题翻译：包含高K电介质层的存储器件
公开(公告)号：US08691647B1
公开(公告)日：2014-04-08
申请号：US10927692
申请日：2004-08-27
申请人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
发明人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.
摘要翻译：在一个实施例中，公开了一种半导体器件。所述半导体器件形成在具有有源区的半导体衬底上，所述半导体器件包括：栅极电介质层，其设置在所述半导体衬底上，所述栅极电介质层具有至少两个具有至少一个具有电介质的子层的子层常数大于SiO2; 形成在所述栅介质层上的浮置栅极，限定插入在所述半导体衬底的有源区域内形成的源极和漏极之间的沟道; 形成在浮动栅极上方的控制栅极; 以及插入在所述浮置栅极和所述控制栅极之间的隔间介电层，所述栅极间介电层包括：形成在所述浮动栅极上的第一层; 形成在所述第一层上的第二层; 以及形成在第二层上的第三层，其中第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数。

62. 发明申请

US20120038051A1 BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME 有权
标题翻译：带硅胶的局部连接器和其制造方法
公开(公告)号：US20120038051A1
公开(公告)日：2012-02-16
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

63. 发明授权

US07811915B2 Method for forming bit lines for semiconductor devices 有权
标题翻译：用于形成半导体器件的位线的方法
公开(公告)号：US07811915B2
公开(公告)日：2010-10-12
申请号：US12048549
申请日：2008-03-14
申请人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
发明人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L21/22
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.
摘要翻译：一种形成半导体器件的方法包括在衬底的第一部分上形成第一介电层，在第一介电层上形成电荷存储层，并蚀刻电荷存储层和第一介电层中的沟槽，其中沟槽延伸到基底。该方法还包括将n型杂质注入到衬底中以形成具有第一深度和第一宽度的n型区域，并且在植入n型杂质之后将p型杂质注入到衬底中，形成p型杂质具有第二深度和第二宽度的p型区域。该方法还包括在电荷存储层上形成第二电介质层，并在第二电介质层上形成控制栅极。

64. 发明授权

US07786003B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US07786003B1
公开(公告)日：2010-08-31
申请号：US11136569
申请日：2005-05-25
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

65. 发明授权

US06927145B1 Bitline hard mask spacer flow for memory cell scaling 有权
标题翻译：位线硬掩模间隔流程用于存储单元缩放
公开(公告)号：US06927145B1
公开(公告)日：2005-08-09
申请号：US10770673
申请日：2004-02-02
申请人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
发明人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
IPC分类号： H01L21/027 , H01L21/761 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和形成半导体器件的方法。半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

66. 发明授权

US06912163B2 Memory device having high work function gate and method of erasing same 有权
标题翻译：具有高功函数门的存储器件及其擦除方法
公开(公告)号：US06912163B2
公开(公告)日：2005-06-28
申请号：US10658506
申请日：2003-09-09
申请人： Wei Zheng , Yun Wu , Hidehiko Shiraiwa , Mark T. Ramsbey , Tazrien Kamal
发明人： Wei Zheng , Yun Wu , Hidehiko Shiraiwa , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L29/7923 , H01L29/7887
摘要： A charge trapping dielectric memory device. The memory device includes a gate electrode disposed over a dielectric stack that includes a dielectric charge trapping layer. The gate electrode has a work function of about 4.6 eV to about 5.2 eV.
摘要翻译：电荷俘获介质存储器件。存储器件包括设置在包括介电电荷捕获层的电介质叠层上的栅电极。栅电极具有约4.6eV至约5.2eV的功函数。

67. 发明授权

US06803272B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices 有权
标题翻译：在改性ONO结构中使用高K介电材料用于半导体器件
公开(公告)号：US06803272B1
公开(公告)日：2004-10-12
申请号：US10646080
申请日：2003-08-22
申请人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
发明人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
IPC分类号： H01L218242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/7923
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.
摘要翻译：一种制造包括修饰的ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一氧化物层; 在所述第一氧化物层上沉积包含高K电介质材料的层; 以及在包含高K电介质材料的层上形成顶部氧化物层。半导体器件可以是例如MIRRORBIT TM 2位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

68. 发明授权

US06541816B2 Planar structure for non-volatile memory devices 失效
公开(公告)号：US06541816B2
公开(公告)日：2003-04-01
申请号：US09893026
申请日：2001-06-27
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi S. Sunkavalli , Janet S. Wang , Narbeh Derhacobian
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi S. Sunkavalli , Janet S. Wang , Narbeh Derhacobian
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

69. 发明授权

US06500713B1 Method for repairing damage to charge trapping dielectric layer from bit line implantation 有权
标题翻译：修复来自位线植入的电荷捕获电介质层损伤的方法
公开(公告)号：US06500713B1
公开(公告)日：2002-12-31
申请号：US10023349
申请日：2001-12-20
申请人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal
发明人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/268 , H01L27/115
摘要： A method of forming a buried bit in line in MONOS cell implants dopant into a substrate through a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer. The implantation process damages the ONO layer. A laser thermal annealing process repairs the damage to the ONO layer, so that leakage between the buried bit line formed during the implantation process and a control gate formed after the laser thermal annealing is complete is avoided.
摘要翻译：在MONOS单元中通过诸如氧化物 - 氧化物 - 氧化物（ONO）层的电荷捕获介电层将掺杂剂埋入衬底中的方法。植入过程损害ONO层。激光热退火工艺修复对ONO层的损伤，从而避免了在注入过程中形成的掩埋位线与在激光热退火之后形成的控制栅极之间的泄漏完成。

70. 发明授权

US06468865B1 Method of simultaneous formation of bitline isolation and periphery oxide 有权
标题翻译：同时形成位线隔离和周边氧化物的方法
公开(公告)号：US06468865B1
公开(公告)日：2002-10-22
申请号：US09723653
申请日：2000-11-28
申请人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.
摘要翻译：本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

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