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1. 发明授权

US08691647B1 Memory devices containing a high-K dielectric layer 有权
标题翻译：包含高K电介质层的存储器件
公开(公告)号：US08691647B1
公开(公告)日：2014-04-08
申请号：US10927692
申请日：2004-08-27
申请人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
发明人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.
摘要翻译：在一个实施例中，公开了一种半导体器件。所述半导体器件形成在具有有源区的半导体衬底上，所述半导体器件包括：栅极电介质层，其设置在所述半导体衬底上，所述栅极电介质层具有至少两个具有至少一个具有电介质的子层的子层常数大于SiO2; 形成在所述栅介质层上的浮置栅极，限定插入在所述半导体衬底的有源区域内形成的源极和漏极之间的沟道; 形成在浮动栅极上方的控制栅极; 以及插入在所述浮置栅极和所述控制栅极之间的隔间介电层，所述栅极间介电层包括：形成在所述浮动栅极上的第一层; 形成在所述第一层上的第二层; 以及形成在第二层上的第三层，其中第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数。

2. 发明授权

US06548855B1 Non-volatile memory dielectric as charge pump dielectric 失效
标题翻译：非易失性存储介质作为电荷泵电介质
公开(公告)号：US06548855B1
公开(公告)日：2003-04-15
申请号：US10147622
申请日：2002-05-16
申请人： Mark T. Ramsbey , Arvind Halliyal , Kuo-Tung Chang , Nicholas H. Tripsas , Wei Zheng , Unsoon Kim
发明人： Mark T. Ramsbey , Arvind Halliyal , Kuo-Tung Chang , Nicholas H. Tripsas , Wei Zheng , Unsoon Kim
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11539
摘要： A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.
摘要翻译：一种用于在电力终止时保留数据的非易失性存储器件。非易失性存储器件包括至少一个存储单元和用于加速输入电压源的电荷泵。电荷泵包括至少一个电容器，其中电荷泵电容器的电介质和存储单元的电介质在相同的处理步骤期间形成。

3. 发明授权

US06639271B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 失效
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06639271B1
公开(公告)日：2003-10-28
申请号：US10027253
申请日：2001-12-20
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L29792
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

4. 发明授权

US07001807B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

5. 发明授权

US06861307B2 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06861307B2
公开(公告)日：2005-03-01
申请号：US10631199
申请日：2003-07-31
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/28 , H01L29/51 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

6. 发明授权

US06693321B1 Replacing layers of an intergate dielectric layer with high-K material for improved scalability 有权
标题翻译：用高K材料代替隔间介电层的层，以提高可扩展性
公开(公告)号：US06693321B1
公开(公告)日：2004-02-17
申请号：US10145952
申请日：2002-05-15
申请人： Wei Zheng , Arvind Halliyal , Mark W. Randolph
发明人： Wei Zheng , Arvind Halliyal , Mark W. Randolph
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/511
摘要： A method of making and a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer and defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer including a first, a second and a third layers. The first layer formed on the floating gate. The second layer formed on the first layer. The third layer formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (Å) of SiO2.
摘要翻译：一种制造方法和形成在具有活性区域的半导体衬底上的半导体器件。半导体器件包括设置在半导体衬底上的栅介质层。在栅极电介质层上形成浮置栅极，并且限定了介于形成在半导体衬底的有源区域内的源极和漏极之间的沟道。控制栅极形成在浮动栅极上方。此外，半导体器件包括介于浮置栅极和控制栅极之间的隔间介电层。隔间介电层包括第一层，第二层和第三层。在浮动门上形成的第一层。形成在第一层上的第二层。形成在第二层上的第三层。第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数和少于约50埃（SiO 2）的电当量厚度。

7. 发明授权

US06630383B1 Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer 有权
标题翻译：双层浮栅，用于改善浮栅和高K电介质层之间的功函数
公开(公告)号：US06630383B1
公开(公告)日：2003-10-07
申请号：US10274063
申请日：2002-10-17
申请人： Effiong Ibok , Wei Zheng , Nicholas H. Tripsas , Mark T. Ramsbey , Fred T K Cheung
发明人： Effiong Ibok , Wei Zheng , Nicholas H. Tripsas , Mark T. Ramsbey , Fred T K Cheung
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/42324 , H01L29/4958 , H01L29/51 , H01L29/511
摘要： In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.
摘要翻译：在一个实施例中，公开了制造栅叠层半导体器件的方法。该方法包括以下步骤：在p型半导体衬底上形成隧道氧化物层; 通过首先形成n型多晶硅层并对n型多晶硅层进行氮化，然后在氮化的n型多晶硅层上形成p型多晶硅层，在隧道氧化物层上形成浮栅; 以及在p型多晶硅层上形成高K绝缘层。

8. 发明授权

US06735123B1 High density dual bit flash memory cell with non planar structure 失效
标题翻译：具有非平面结构的高密度双位闪存单元
公开(公告)号：US06735123B1
公开(公告)日：2004-05-11
申请号：US10164895
申请日：2002-06-07
申请人： Nicholas H. Tripsas , Mark T. Ramsbey , Wei Zheng , Effiong Ibok , Fred T K Cheung
发明人： Nicholas H. Tripsas , Mark T. Ramsbey , Wei Zheng , Effiong Ibok , Fred T K Cheung
IPC分类号： G11C1604
CPC分类号： H01L29/66833 , G11C16/0475 , H01L21/28282 , H01L29/7923 , Y10S438/981
摘要： A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.
摘要翻译：双位电介质存储单元包括具有源极区和衬底的衬底，衬底在中心沟道区的相对侧上。多电荷电荷捕获电介质位于中心通道区域上方的衬底上，并且包括在相对的源侧向区域和漏极侧向区域之间的中心区域。控制栅极位于多电平电荷捕获电介质的上方。多电荷电荷俘获电介质包括邻近衬底的隧道电介质层，邻近控制栅极的顶部电介质和位于其间的电荷捕获电介质。中心区域中的隧道介电层的厚度大于源极横向区域和漏极侧向区域中的每一个中的隧道介电层的厚度。

9. 发明授权

US06912163B2 Memory device having high work function gate and method of erasing same 有权
标题翻译：具有高功函数门的存储器件及其擦除方法
公开(公告)号：US06912163B2
公开(公告)日：2005-06-28
申请号：US10658506
申请日：2003-09-09
申请人： Wei Zheng , Yun Wu , Hidehiko Shiraiwa , Mark T. Ramsbey , Tazrien Kamal
发明人： Wei Zheng , Yun Wu , Hidehiko Shiraiwa , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L29/7923 , H01L29/7887
摘要： A charge trapping dielectric memory device. The memory device includes a gate electrode disposed over a dielectric stack that includes a dielectric charge trapping layer. The gate electrode has a work function of about 4.6 eV to about 5.2 eV.
摘要翻译：电荷俘获介质存储器件。存储器件包括设置在包括介电电荷捕获层的电介质叠层上的栅电极。栅电极具有约4.6eV至约5.2eV的功函数。

10. 发明授权

US09446048B2 Methods for treating leukemia and disorders mediated by CBFβ and RUNX1 proteins 有权
标题翻译：用于治疗白血病和由CBFβ和RUNX1蛋白介导的病症的方法
公开(公告)号：US09446048B2
公开(公告)日：2016-09-20
申请号：US14005534
申请日：2012-03-15
申请人： Pu Liu , Wei Zheng , Juan Marugan , Noel T. Southall , Lea Cunningham
发明人： Pu Liu , Wei Zheng , Juan Marugan , Noel T. Southall , Lea Cunningham
IPC分类号： A61K31/40 , A61K31/5513 , A61K31/203 , A61K31/417 , A61K31/704 , A61K31/7068 , A61K31/7076 , A61K45/06 , A61K38/20
CPC分类号： A61K31/5513 , A61K31/203 , A61K31/40 , A61K31/417 , A61K31/704 , A61K31/7068 , A61K31/7076 , A61K38/2013 , A61K45/06 , Y10S514/908 , A61K2300/00
摘要： A method for treating core binding factor (CBF) leukemia in a subject, comprising administering to a subject having CBF leukemia a therapeutically effective amount of a compound, or a pharmaceutically acceptable salt or ester thereof, that inhibits CBFβ and RUNX1 binding in the subject, thereby treating the CBF leukemia.
摘要翻译：一种用于治疗受试者中的核心结合因子（CBF）白血病的方法，包括向具有CBF白血病的受试者施用治疗有效量的在受试者中抑制CBFβ和RUNX1结合的化合物或其药学上可接受的盐或酯，从而治疗CBF白血病。

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